Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 17:55:19 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
178 Commits 4 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
ddaf67c043
Go to file
Noah Boorstin ddaf67c043 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined busybear: preload bootram 2021-02-24 18:46:09 +00:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to. 2021-02-14 08:58:33 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor