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Configurable RISC-V Processor
224 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
2769b147cb
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Noah Boorstin 2769b147cb busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor