Ross Thompson
6734685333
Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
2024-07-09 19:04:18 -05:00
Ross Thompson
ccf4bb8ddc
Maybe have the incircuit trigger working.
2024-06-26 16:15:46 -07:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
...
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Ross Thompson
c9f51df34a
Fixed bug in rvvi reset.
2024-06-12 14:47:32 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Rose Thompson
6a4c8667df
Added new signals to ILA to debug the RVVI tracer.
...
The tracer appears to be stuck and the CPU is never getting out of (into reset).
2024-05-30 16:43:25 -05:00
Jacob Pease
3f7659c8ad
Removed old fpgaTop.v file.
2024-05-30 16:15:19 -05:00
Jacob Pease
7ecd1c7d5f
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
2024-05-30 15:48:27 -05:00
Rose Thompson
9703055758
The FPGA is synthesizing with the rvvi and ethernet hardware.
2024-05-30 15:37:17 -05:00
Rose Thompson
7693c5d4e2
Updates to fpga top level.
2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388
Replaced fpga's verilog top with system verilog.
2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c
Replaced fpga top level verilog with system verilog.
2023-12-15 13:07:08 -06:00
Jacob Pease
87e6a5ccf2
Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
2023-11-18 19:15:39 -06:00
Ross Thompson
d33c966a42
Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.
2023-10-10 17:46:12 -05:00
Jacob Pease
2bf6207919
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Jacob Pease
b626f2185a
Fixed GPIO pin names in fpgaTop.v
2023-07-25 20:57:04 -05:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
63afd95ad3
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
ab6ef5bb58
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
2752e5de4c
Fixed a bunch of timing constraints for the arty a7 board.
2023-07-19 17:08:16 -05:00
Ross Thompson
97a16f75dc
Fixed typo in fpga top for arty a7.
2023-07-19 11:37:29 -05:00
Ross Thompson
e4d6a9f8c6
Removed all old configuration files.
2023-07-19 10:28:54 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
6a2b752fc0
Updated arty a7 fpga top.
2023-07-17 15:55:57 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Ross Thompson
a8f11dcad0
FPGA updates.
2023-06-20 11:11:34 -05:00
Ross Thompson
1a23f1360f
Updated fpga wally wrapper to work with the ILA.
2023-06-19 12:15:48 -05:00
Ross Thompson
443c568994
Vivado requires an intermediate wrapper file for parameterization.
2023-06-16 16:30:14 -05:00
Ross Thompson
c44d4321fb
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
1fec535b32
Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram.
...
but the data is wrong.
2023-04-19 10:35:18 -05:00
Ross Thompson
224bf74530
Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed.
2023-04-18 17:45:41 -05:00
Ross Thompson
668e69fdc9
Added more signals to debugger in hopes I can figure out why the mig is not responding.
2023-04-18 15:51:52 -05:00
Jacob Pease
2839f4f41a
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Ross Thompson
3588c53e66
It's almost working.
2023-04-18 14:24:59 -05:00
Ross Thompson
deb0bfc24d
Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
2023-04-17 20:05:59 -05:00
Ross Thompson
fbbba0e5c2
Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8.
2023-04-17 18:39:25 -05:00
Ross Thompson
2cbaa5c27b
Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way.
2023-04-17 16:37:18 -05:00
Ross Thompson
480562e53e
Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there.
2023-04-17 16:00:02 -05:00
Ross Thompson
f4734c0d1b
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
5bcb0f6ace
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
0700202001
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Jacob Pease
b796b1b492
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Ross Thompson
0afba56927
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Jacob Pease
2d0199a354
Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
2023-03-24 17:01:27 -05:00
Jacob Pease
449b835fcd
Disabled old SD card and attached IOBUF's to new SD peripheral.
2023-02-28 12:20:46 -06:00
