910 Commits

Author	SHA1	Message	Date
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
Rose Thompson	a6995af91c	Fixed bug in uncore updates which broke SDC.	2023-11-13 16:15:23 -06:00
Rose Thompson	707b0c557c	Cleanup and optimization of Zicclsm.	2023-11-13 14:28:22 -06:00
Rose Thompson	cc7a0b211a	Cleanup.	2023-11-13 12:35:11 -06:00
Rose Thompson	c8cca8dfb8	Simplification.	2023-11-10 18:39:36 -06:00
Rose Thompson	c0e02ae190	Found another bug in the RTL's Zicclsm alignment.	2023-11-10 18:26:55 -06:00
Rose Thompson	02ab9fe99c	Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.	2023-11-10 17:58:42 -06:00
Rose Thompson	84d86b1994	Fixed spill bugs in the aligner.	2023-11-10 17:18:45 -06:00
Rose Thompson	b74bfbeefd	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
Rose Thompson	9abd26aad9	Fixed bug which broke the non Zicclsm configs.	2023-11-10 16:08:04 -06:00
naichewa	5ce16dcb63	Cleanup	2023-11-09 16:52:55 -08:00
naichewa	3052a68d84	Remove old 2/4 bit logic, add comments, ... clean up unused signals	2023-11-09 16:48:11 -08:00
naichewa	b13b8feee4	updated to-do comments	2023-11-08 15:28:51 -08:00
naichewa	d67badfc60	fix hardware interlock, hold mode deassert	2023-11-08 15:20:51 -08:00
Rose Thompson	44c60a3e76	Merge pull request #455 from davidharrishmc/dev ... Bit manipulation imperas config, fsqrt code changes to match chapter	2023-11-08 08:27:15 -08:00
naichewa	a5837eb62c	fifo fixes and edge case testing	2023-11-07 17:59:46 -08:00
David Harris	637cc3b78a	Reparitioned sign logic in fdivsqrt to match paper	2023-11-06 14:11:42 -08:00
David Harris	4de21c206f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-03 16:04:10 -07:00
naichewa	6cdeb671bb	Merge branch 'main' into spi	2023-11-03 13:15:15 -07:00
David Harris	7a56a66927	set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t	2023-11-03 06:37:05 -07:00
David Harris	1f2899de14	Modified rams to take USE_SRAM rather than P to facilitate synthesis	2023-11-03 05:44:13 -07:00
David Harris	dd072c80f2	Updated testbenches to capture InstrM because it may be optimized out of IFU	2023-11-03 05:24:15 -07:00
David Harris	402538e13c	Temporary fix of InstrM to prevent testbench hanging	2023-11-03 04:59:44 -07:00
David Harris	09aebbf252	Fixed regression error of watchdog timeout when PCM is optimized out of the IFU	2023-11-03 04:38:27 -07:00
naichewa	29e42b21df	added test cases	2023-11-02 15:42:28 -07:00
Rose Thompson	0a4ed5515b	Merge branch 'main' into Zicclsm	2023-11-02 12:55:51 -05:00
Rose Thompson	13333d3e82	Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup.	2023-11-01 14:25:18 -05:00
naichewa	a08356fdaa	correct exclusion tags and reset testbench	2023-11-01 10:34:39 -07:00
naichewa	e3d8162279	harris code review 3	2023-11-01 10:14:15 -07:00
David Harris	31d9ec08cb	Improved comments about memory read paths	2023-11-01 07:00:17 -07:00
naichewa	9aa8a7af3e	comments, more test cases	2023-11-01 01:26:34 -07:00
Rose Thompson	5660eff57d	Working through issues with the psill logic.	2023-10-31 18:50:13 -05:00
naichewa	fefb5adb8f	code review harris	2023-10-31 12:27:41 -07:00
David Harris	680fb3f30b	Conditionally instantiate hardware in ifu	2023-10-30 20:55:00 -07:00
David Harris	afabc52b61	Gated InstrOrigM and PCMReg when not needed	2023-10-30 20:05:37 -07:00
David Harris	2d17a991d8	rom1p1r code cleanup	2023-10-30 19:47:49 -07:00
David Harris	3f7c67882f	rom1p1r code cleanup	2023-10-30 19:46:38 -07:00
David Harris	90a178e31e	Made 2-bit AdrReg conditional on being needed	2023-10-30 19:13:43 -07:00
naichewa	7dd3f24d6c	Merge branch 'main' into spi	2023-10-30 17:01:41 -07:00
naichewa	2330f4ee63	hardware interlock	2023-10-30 17:00:20 -07:00
Rose Thompson	2241976d29	Updated mmu to not generate trap on cacheable misaligned access when supported. ... Updated tests with David's help.	2023-10-30 18:26:11 -05:00
Rose Thompson	f13b67b869	Preemptively fixed the bytemask bug before testing.	2023-10-30 15:47:46 -05:00
Rose Thompson	b5763e11e8	rv32gc now also works with the alignment module. Still not tested with misligned access.	2023-10-30 15:30:09 -05:00
Rose Thompson	9cd2e47783	Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests.	2023-10-30 14:54:58 -05:00
Rose Thompson	569e3dc906	Finally lints cleanly.	2023-10-30 14:00:49 -05:00
David Harris	f6a7f707bd	Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.	2023-10-30 09:56:17 -07:00
David Harris	27b8ebb9bd	Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.	2023-10-30 07:06:34 -07:00
Rose Thompson	dce3c85105	Progress.	2023-10-27 16:31:22 -05:00
Rose Thompson	747f453bb5	Passes lint with some exceptions. Still need to add misaligned store support.	2023-10-27 14:41:42 -05:00
Rose Thompson	36ca64c567	At least have the aligner integrated, but not tested.	2023-10-27 13:55:16 -05:00