Rose Thompson
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77d47e531f
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Merge branch 'main' into lrufixes
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2024-11-13 10:34:21 -06:00 |
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Rose Thompson
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2fe73f8174
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Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.
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2024-11-13 00:02:51 -06:00 |
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Rose Thompson
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8993432928
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Resolved issue with questa not liking the TEST +arg as a generate.
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2024-11-12 23:57:30 -06:00 |
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Rose Thompson
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ef7072b7c2
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Merge branch 'main' into lrufixes
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2024-11-12 17:57:28 -06:00 |
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Rose Thompson
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8659d6efdb
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Resolved all CacheSim.py vs Wally mismaches.
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2024-11-12 17:24:06 -06:00 |
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Rose Thompson
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57fbd35484
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Fixed lint errors in loggers.sv with Kaitlin.
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2024-11-12 15:03:30 -06:00 |
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Rose Thompson
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b7b7c79726
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CBO.FLUSH was not clearing the valid bit if the cacheline was clean.
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2024-11-12 14:16:55 -06:00 |
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Rose Thompson
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5cc1fd4a85
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Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.
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2024-11-12 12:08:14 -06:00 |
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Rose Thompson
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8a4868ac57
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Resolved a bug in the cache but there are still mismatches with the cache simulator.
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2024-11-12 11:35:29 -06:00 |
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Rose Thompson
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0cf7b2e45a
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Progress on fixing the cache simulator to support cbo instructions.
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2024-11-11 16:37:17 -06:00 |
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Rose Thompson
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8fb1673ab3
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Updated email address authorship for my files.
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2024-10-15 10:27:53 -05:00 |
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Rose Thompson
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113d71f1a0
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More name updates.
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2024-08-21 10:51:24 -07:00 |
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Rose Thompson
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f603d21826
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Updated my name in multiple locations.
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2024-08-21 10:50:39 -07:00 |
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David Harris
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312c9c9f55
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Updated logger to new IClass signal name
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2024-06-12 07:24:05 -07:00 |
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Jordan Carlin
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ef778da98d
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Eliminate more logical operators and replace with bitwise
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2024-05-15 10:50:23 -07:00 |
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David Harris
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ac9a21873d
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Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
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2024-04-06 10:34:21 -07:00 |
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Rose Thompson
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081cf5be55
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Fixed the CacheHit logger bug.
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2024-03-28 13:40:01 -05:00 |
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David Harris
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aff61ea97a
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Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
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2023-12-13 11:33:59 -08:00 |
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David Harris
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1f57df7f8b
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Fixed reference to deleted atomic signal in cache
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2023-11-23 20:29:10 -08:00 |
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Rose Thompson
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bc935b1b3b
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Fixed second bug in the logger script when branch logging enabled but counter logger not.
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2023-11-15 14:56:02 -06:00 |
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Rose Thompson
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5d4a89b27c
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Fixed bug in the btb branch logging.
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
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2023-11-15 14:51:47 -06:00 |
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David Harris
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bddd2d573e
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Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
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2023-11-05 07:06:53 -08:00 |
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Ross Thompson
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59022099c7
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Fixed the icache and dcache overlogging issue.
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2023-07-14 15:47:05 -05:00 |
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Ross Thompson
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27f6f00402
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Changes for xcelium.
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2023-07-07 18:22:28 -05:00 |
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Ross Thompson
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85567841eb
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Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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Ross Thompson
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301d54fea8
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Significant refactoring of testbench.
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2023-06-14 17:02:49 -05:00 |
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