bbracker
7a652139b5
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
bbracker
3f6b018f66
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-16 16:17:53 -04:00
bracker
d1bab12e1e
chmod +x'd privileged testgen scripts
2021-06-16 10:28:57 -05:00
bbracker
8d8d2aabc2
fixed incorrect expectation fof CLINT spec
2021-06-15 19:24:24 -04:00
bbracker
6f1f585c2c
Merge remote-tracking branch 'origin/fixPrivTests' into main
2021-06-15 09:57:46 -04:00
Katherine Parry
920ff984ca
Updated FMA
2021-06-14 13:42:53 -04:00
David Harris
5e01f71c52
disabled Verilator WIDTH warnings in ICCacheCntrl
2021-06-12 19:50:06 -04:00
Ross Thompson
5d7ca87982
fixed the mtime register.
2021-06-11 13:50:13 -05:00
James E. Stine
171a6728b0
Put repository of fpdivsqrt with RTL-based adder instead of structural implementation
2021-06-11 14:35:22 -04:00
bracker
11a84f64b8
attempt no 1: just change out x28s for x31s
2021-06-11 12:39:28 -05:00
David Harris
79ee817d91
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
David Harris
690e2b7f31
Restored counter events
2021-06-10 11:18:58 -04:00
David Harris
0e4e091a39
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-10 10:47:55 -04:00
David Harris
c3d106f0f0
Removed two cycles of latency from the DTIM
2021-06-10 10:30:24 -04:00
bbracker
9c3cb0d2bf
peripheral lint fixes
2021-06-10 10:19:10 -04:00
bbracker
f0266f621b
merge
2021-06-10 10:03:01 -04:00
bbracker
31e1c926f2
attempt to fix regression by adding PMP_ENTRIES to configs
2021-06-10 09:59:26 -04:00
bbracker
3e7126e0c2
buildroot progress -- able to mimic GDB output
2021-06-10 09:58:20 -04:00
bbracker
58d0e46d02
UART improved and added more reg read side effects
2021-06-10 09:53:48 -04:00
David Harris
17b76d4cd7
Configurable number of performance counters
2021-06-10 09:41:26 -04:00
David Harris
6dcf86948c
Restored PCCorrectE declaration in IFU
2021-06-09 21:09:16 -04:00
David Harris
e231fc6b00
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
David Harris
3fb378dcf0
removed verilator lint_off WIDTH
2021-06-09 21:01:44 -04:00
David Harris
9dd3857c26
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
David Harris
4bd7058456
More PMP entries
2021-06-08 15:33:06 -04:00
David Harris
9a17556de4
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
fcb9b1f0e1
working version with new mmu comments, old boottim values
2021-06-08 15:20:25 -04:00
Kip Macsai-Goren
b37eebfe4d
merge of reverted main into up to date main
2021-06-08 14:57:43 -04:00
Kip Macsai-Goren
3b5627b753
reverted to working version with new mmu comments
2021-06-08 14:56:00 -04:00
David Harris
cfe5c27946
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
Kip Macsai-Goren
6ed96761b6
Merge small mmu changes into main
2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
be99c18002
making mmu branch line up with main
2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
41ceb20296
some cleanup of signals, not done yet
2021-06-08 13:39:32 -04:00
bbracker
17960a6484
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
5026a42fac
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
e044f72e59
remove redundant decodes, fixed mmu logic ins/outs
2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
146ed95bdb
got rid of some underscores in filenames, modules
2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
46b2b19792
implemented simpler page mixers, cleaned up a bit
2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
55d50f5607
began updating cam line to reduce muxes, confusion
2021-06-07 17:03:31 -04:00
Kip Macsai-Goren
1377680270
regression working partially done page mask
2021-06-07 17:02:31 -04:00
David Harris
4740ef97d6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-07 16:14:13 -04:00
David Harris
c3d21967f8
Simplified superpage matching
2021-06-07 16:11:28 -04:00
Katherine Parry
b55798f09b
lint is clean
2021-06-07 14:22:54 -04:00
bbracker
3e11da2aa2
temporarily removing buildroot from regression until it is regenerated
2021-06-07 13:20:50 -04:00
David Harris
b37bcc8e38
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
95cc70295b
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
d69501c4fa
Cleaned up some unused signals
2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
b99b5f8e0e
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
4a00fbaf04
Merge branch 'mmu' into main
...
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
318a547531
added shared constants file list of includes
2021-06-04 17:05:47 -04:00
Kip Macsai-Goren
7e41b17e65
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
Ross Thompson
6f58c66be8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-04 15:16:39 -05:00
Ross Thompson
e200b4b5a4
Continued I-Cache cleanup.
...
Removed strange mux on InstrRawD along with
the select logic.
2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2
Moved I-Cache offset selection mux to icache.sv (top level).
...
When we switch to set associative this is will be more efficient.
2021-06-04 13:49:33 -05:00
Ross Thompson
fdc7c673dd
Cleaned up the I-Cache memory.
2021-06-04 13:36:06 -05:00
Katherine Parry
19116ed889
Double-precision FMA instructions
2021-06-04 14:00:11 -04:00
Ross Thompson
2c16591396
Reorganized the icache names.
2021-06-04 12:53:42 -05:00
Ross Thompson
147be536f1
Relocated the icache to the cache directoy.
2021-06-04 12:23:46 -05:00
David Harris
b836679ae1
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
99d661cee9
Fixed RV32 MMU constants
2021-06-04 09:15:42 -04:00
David Harris
a61411995a
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
1b2822e078
added support for sv48 and some docs on how to use these files
2021-06-03 14:32:12 -04:00
Kip Macsai-Goren
a84dd6dfc5
added tests for SV48 and translation off with vmem
2021-06-03 14:28:52 -04:00
bbracker
d8913e5547
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-03 10:03:26 -04:00
bbracker
8338b3bd34
expanded GPIO testing and caught small GPIO bug
2021-06-03 10:03:09 -04:00
Ross Thompson
db2a38c300
Fixed a few lint errors,
...
clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
bbracker
4f03ecb6ec
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-02 10:03:23 -04:00
bbracker
28abd28b1f
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
f7deda0514
implemented Sv48.
2021-06-01 17:50:37 -04:00
Kip Macsai-Goren
06cf3a8403
Edited and added constants to support SV48
2021-06-01 17:49:45 -04:00
James E. Stine
7f5e5287b0
delete div.bak
2021-06-01 17:39:54 -04:00
Ross Thompson
2093e7cce3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3
Minor cosmetic update to fpu.sv
2021-06-01 15:45:32 -04:00
James E. Stine
bccdd2c137
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
8e330367ac
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
Ross Thompson
605ceb7ddb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 12:42:21 -05:00
Ross Thompson
f5aa5d7c67
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
8f7e69715d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-01 13:20:39 -04:00
Ross Thompson
9a49cf74c3
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
8f9680556f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
Ross Thompson
1db8d0e59c
may have fixed the global branch history predictor.
...
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
42af5f9818
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-31 11:01:15 -04:00
James E. Stine
a71b97e878
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
James E. Stine
889b935630
Modify elements of generics for LZD and shifter wrote for integer
...
divider.
2021-05-31 08:36:19 -04:00
bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
529226ac8d
made priority encoder parameterizable
2021-05-28 18:09:28 -04:00
Ross Thompson
40bdcda32d
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Katherine Parry
0646e08609
classify unit created and passes imperas tests
2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb
FADD and FSUB imperas tests pass
2021-05-26 12:33:33 -04:00
James E. Stine
e3b3321f91
delete old file for FPregfile
2021-05-26 09:13:09 -05:00
James E. Stine
cc2a7ced7f
Add regression test for fpadd
2021-05-26 09:12:37 -05:00
Katherine Parry
3869a73a9c
renamed top level FPU wires
2021-05-25 20:04:34 -04:00
