James E. Stine 2c140679e3 Minor cosmetic update to fpu.sv		2021-06-01 15:45:32 -04:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Updates to muldiv.sv for 32-bit div/rem	2021-06-01 15:31:07 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
src	Minor cosmetic update to fpu.sv	2021-06-01 15:45:32 -04:00
testbench	Updates to muldiv.sv for 32-bit div/rem	2021-06-01 15:31:07 -04:00
testgen	Forgot to add csr permission tests to testbench	2021-05-04 20:20:22 -04:00
lint-wally	slightly more path independence for using verilator	2021-05-24 18:11:56 -04:00