34 Commits

Author	SHA1	Message	Date
James Stine	c660403ff2	Add back SV for integer division to use 8-bit CPA in qslc	2022-06-15 11:46:39 -05:00
James Stine	a078015271	Add r=4 C code	2022-06-15 11:44:09 -05:00
David Harris	9e1ec0255f	Removed SRT testvectors from repo	2022-06-13 19:27:33 +00:00
stineje	d3ad512d3c	Update integer division for r4 and qslc_r4a2.c	2022-06-09 16:45:13 -05:00
David Harris	5612ca7041	qslc_r4a2 generator	2022-06-09 17:26:47 +00:00
cturek	0e308cfccc	Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench.	2022-06-04 00:14:10 +00:00
cturek	e3a0ee333f	Fixed typos	2022-06-01 00:07:36 +00:00
David Harris	80315fedff	fixed merge conflicts	2022-05-28 09:44:55 +00:00
David Harris	4335895b21	Added comments to some files, added a+b = 0 detector to comparator.sv	2022-05-28 09:41:48 +00:00
cturek	f7a3855af1	fixed sizing issues in expcalc	2022-05-26 22:35:17 +00:00
cturek	a025014650	Implemented on-the-fly conversion for unsigned numbers	2022-05-26 22:20:43 +00:00
cturek	0f1da722bf	Set up the divider for on-the-fly conversion	2022-05-26 16:45:28 +00:00
cturek	366cd5f1d5	Renamed variables for readability	2022-05-26 00:01:51 +00:00
cturek	650779318d	Fixed exponent verification, added sign module and added sign tests	2022-05-25 23:36:21 +00:00
Katherine Parry	18bdaf0179	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-23 23:11:41 +00:00
Katherine Parry	37e74648a9	added exponents to srt divider	2022-05-23 23:07:27 +00:00
David Harris	2d175e2a37	Checked in qst2.c from James	2022-05-23 20:26:05 +00:00
David Harris	20c861ee6f	Restored srt to working without exponent unit	2022-05-17 15:09:48 +00:00
David Harris	b992a61ca3	removed exptestgen	2022-05-17 00:06:44 +00:00
David Harris	7aba83a35c	Cleaned up unpacker changes in srt and lint errors	2022-05-17 00:06:14 +00:00
David Harris	f314e60dc8	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
ushakya22	67780305ae	Moved order of reading a, b, and result from test vectors file so that result ... matches up with inputs a and b	2022-02-21 17:28:11 +00:00
ushakya22	88060a74f5	- created new testbench file instead of having it at the bottom of the srt file ... - uses unpacker to parse 64 bit floating point numbers - updated testbench to read from new testvectors generated by exptestbench Notes: MEM_WIDTH updated to be 64*3 Input numbers and output result is 64 bit number MEM_SIZE set to 60000	2022-02-21 16:24:50 +00:00
ushakya22	d1089163a9	- Created exponent divsion module ... - top module includes exponent module now Notes: - may be a better implementation of the exponent module rather than having what I believe are two adders currently	2022-02-21 16:13:30 +00:00
ushakya22	c6bd51a707	Changed Makefile to compile exptestgen instead of testgen	2022-02-21 16:08:45 +00:00
ushakya22	08d997d68b	reverted srt_standford back to original file pre modifications by Udeema	2022-02-21 16:08:09 +00:00
ushakya22	1495f6ac70	verilator lint for srt	2022-02-21 16:05:43 +00:00
ushakya22	5b83ad0929	Created test vector generation file for exponent and mantissa division	2022-02-21 16:04:41 +00:00
David Harris	143eb0ae65	srt fixes	2022-02-14 18:40:27 +00:00
David Harris	3598e05998	srt batch files	2022-02-14 18:37:46 +00:00
ushakya22	df561f8550	work in progress exponent handling	2022-02-14 18:24:29 +00:00
ushakya22	a996a5e16c	Added unpacker into testbench for srt	2022-02-12 22:05:18 +00:00
David Harris	e3f6c398b5	Mixed C and assembly language test cases; SRT initial version passing tests	2022-01-13 21:45:54 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00