ushakya22 88060a74f5 - created new testbench file instead of having it at the bottom of the srt file ... - uses unpacker to parse 64 bit floating point numbers - updated testbench to read from new testvectors generated by exptestbench Notes: MEM_WIDTH updated to be 64*3 Input numbers and output result is 64 bit number MEM_SIZE set to 60000		2022-02-21 16:24:50 +00:00
..
exptestgen	Created test vector generation file for exponent and mantissa division	2022-02-21 16:04:41 +00:00
exptestgen.c	Created test vector generation file for exponent and mantissa division	2022-02-21 16:04:41 +00:00
lint-srt	verilator lint for srt	2022-02-21 16:05:43 +00:00
Makefile	Changed Makefile to compile exptestgen instead of testgen	2022-02-21 16:08:45 +00:00
sim-srt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-srt-batch	srt batch files	2022-02-14 18:37:46 +00:00
sqrttestgen	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sqrttestgen.c	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sqrttestvectors	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
srt_stanford.sv	reverted srt_standford back to original file pre modifications by Udeema	2022-02-21 16:08:09 +00:00
srt-waves.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
srt.do	srt fixes	2022-02-14 18:40:27 +00:00
srt.sv	- Created exponent divsion module	2022-02-21 16:13:30 +00:00
testbench.sv	- created new testbench file instead of having it at the bottom of the srt file	2022-02-21 16:24:50 +00:00
testgen	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
testgen.c	work in progress exponent handling	2022-02-14 18:24:29 +00:00
testvectors	- created new testbench file instead of having it at the bottom of the srt file	2022-02-21 16:24:50 +00:00