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852 Commits

Author SHA1 Message Date
James E. Stine
7f5e5287b0 delete div.bak 2021-06-01 17:39:54 -04:00
Ross Thompson
2093e7cce3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877 The clock gater was not implemented correctly. Now it is level sensitive to a low clock. 2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3 Minor cosmetic update to fpu.sv 2021-06-01 15:45:32 -04:00
James E. Stine
bccdd2c137 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
Ross Thompson
8e330367ac added clock gater to floating point divider to speed up simulation time. 2021-06-01 13:46:21 -05:00
Ross Thompson
605ceb7ddb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 12:42:21 -05:00
Ross Thompson
f5aa5d7c67 Forgot to include the new gshare predictor file. 2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
8f7e69715d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-01 13:20:39 -04:00
Ross Thompson
9a49cf74c3 Changed to bp config to use gshare. 2021-06-01 12:14:58 -05:00
Ross Thompson
8f9680556f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346 Now have global history working correctly. 2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
Ross Thompson
1db8d0e59c may have fixed the global branch history predictor. 
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
 2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
42af5f9818 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-31 11:01:15 -04:00
James E. Stine
a71b97e878 Cosmetic changes on integer divider 2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07 Add enhancements to integer divider including: 
- better comments
  - optimize FSM to end earlier
  - passes for 32-bit or 64-bit depending on parameter to intdiv

Left div.bak in just in case have to revert back to original for now.
 2021-05-31 09:12:21 -04:00
James E. Stine
889b935630 Modify elements of generics for LZD and shifter wrote for integer 
divider.
 2021-05-31 08:36:19 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
529226ac8d made priority encoder parameterizable 2021-05-28 18:09:28 -04:00
Ross Thompson
40bdcda32d It's a bit sloppy, but the global history predictor is working correctly now. 
There were two major bugs with the predictor.
First the update mechanism was completely wrong.  The PHT is updated with the GHR that was used to lookup the prediction.  PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted.  This is important so that back to back branches' GHRs are not the same.  The must be different to avoid aliasing.  Speculation of the GHR update allows them to be different.  On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed.  Updates to follow.
 2021-05-27 23:06:28 -05:00
Katherine Parry
0646e08609 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6 All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
James E. Stine
e3b3321f91 delete old file for FPregfile 2021-05-26 09:13:09 -05:00
James E. Stine
cc2a7ced7f Add regression test for fpadd 2021-05-26 09:12:37 -05:00
Katherine Parry
3869a73a9c renamed top level FPU wires 2021-05-25 20:04:34 -04:00
Kip Macsai-Goren
32923cb250 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-25 15:28:19 -04:00
Ross Thompson
735e511073 fixed bug with icache miss spill fsm branch. 2021-05-25 14:26:22 -05:00
James E. Stine
e32e812f6a Update FPregfile to use more compact code and better structure for ease in reading 2021-05-25 13:21:59 -05:00
Ross Thompson
aa9a81b760 Merge remote-tracking branch 'refs/remotes/origin/main' into main 2021-05-24 23:25:36 -05:00
Ross Thompson
13034c7406 Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF. 2021-05-24 23:24:54 -05:00
Kip Macsai-Goren
ba134eb166 partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields 2021-05-24 20:59:26 -04:00
James E. Stine
bbc1dfb309 Minor cosmetic elements on div.sv 2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
bbracker
82a6ee4c0e slightly more path independence for using verilator 2021-05-24 18:11:56 -04:00
Ross Thompson
3c5e87d6c2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Ross Thompson
dd26b754eb Fixed minor bug in instruction class decoding. 2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). 2021-05-24 12:37:16 -05:00
Ross Thompson
daf344f1ba Updated branch predictor tests/benchmarks. 2021-05-24 11:13:33 -05:00
James E. Stine
194c32defa Update header for FPadd 2021-05-24 08:28:16 -05:00
Katherine Parry
55f22979ca FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
bbracker
142b02b30a improved PLIC test organization 2021-05-21 15:13:02 -04:00
James E. Stine
49a4097d97 Minor testbench updates to rv64icfd 2021-05-21 09:41:21 -05:00
James E. Stine
47487a625f Update to testbench-imperase for rv64icfd 2021-05-21 09:28:44 -05:00
James E. Stine
694e21541b Update to FLD/FSD testbench 2021-05-21 09:26:55 -05:00
James E. Stine
474d479280 Update to rv64icfd wally-config to run through FP tests 2021-05-21 09:22:17 -05:00
Katherine Parry
67a41748ba FMV.D.X imperas test passes 2021-05-20 22:18:33 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
114bba8370 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
bbracker
8554f2f3cd plic implementation optimizations 2021-05-19 18:10:48 +00:00
bbracker
fd4fae0406 commented out MSTATUS test 2021-05-19 12:38:01 -04:00
James E. Stine
058b265d18 Update rv64icfd batch script 2021-05-18 16:01:53 -05:00
James E. Stine
f407bee5ae Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
bbracker
18ab9015f9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-18 14:33:40 -04:00
bbracker
f43ea946aa changed lint script to use absolute path for verilator because cron jobs stink at using paths 2021-05-18 14:33:22 -04:00
David Harris
7dcc53dcf5 fixed rv64mmu makefile 2021-05-18 14:25:55 -04:00
David Harris
5f214d60b6 Removed rv64wally 2021-05-18 14:08:46 -04:00
David Harris
433ea61d9e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/regression/vish_stacktrace.vstf
 2021-05-18 14:01:19 -04:00
Katherine Parry
409438bc95 floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
bbracker
86d55cd07a fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
69ef758e78 regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
David Harris
1aa1908994 Deleted vish_stacktrace 2021-05-17 18:39:01 -04:00
James E. Stine
49cc330bd9 Forgot initialization config for div - apologies 2021-05-17 17:12:27 -05:00
Elizabeth Hedenberg
853c9243c1 commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
James E. Stine
96eca3287f Add 32/64-bit shifter for update to shifter block 2021-05-17 17:02:13 -05:00
James E. Stine
8822bdd6ad Cleanup of regression 2021-05-17 16:58:15 -05:00
James E. Stine
41da78e0b6 Mod Imperas Testbench for updated Div/Rem 2021-05-17 16:56:30 -05:00
James E. Stine
97cbdae674 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e Fix comment 2021-05-14 08:06:07 -04:00
Thomas Fleming
a191978a97 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-14 07:40:08 -04:00
Thomas Fleming
1fc607b399 Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Thomas Fleming
980c00fa64 Clean up MMU code 2021-05-14 07:12:32 -04:00
Elizabeth Hedenberg
0fe798d5e1 pushing coremark to main branch 2021-05-11 21:33:39 -04:00
Jarred Allen
dc41623754 Minor fixes in regression 2021-05-09 13:57:09 -04:00
Jarred Allen
788680fa4d Fix bug in regression script 2021-05-06 12:56:57 -04:00
Domenico Ottolia
f78f865e88 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 20:22:31 -04:00
Domenico Ottolia
1c884338b0 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
Jarred Allen
15da77fe15 Clean up regression script and document it 2021-05-04 18:58:59 -04:00
ushakya22
6274c8cb80 Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Thomas Fleming
1e0a5ef807 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 15:22:21 -04:00
bbracker
535046e494 small synthesis fixes 2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500 Fix compiler warning in PMP checker 2021-05-04 15:18:08 -04:00
Domenico Ottolia
14becde792 Re-add medeleg tests to testbench 2021-05-04 14:42:20 -04:00
Ross Thompson
619dcb165d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 13:04:20 -05:00
Ross Thompson
2aa4db470b Fixed synthesis bug with icache valid bit. 2021-05-04 13:03:08 -05:00
ushakya22
6a71aafadc Updated CSR tests 2021-05-04 13:48:47 -04:00
Ross Thompson
87d3869a6e Fixed icache pcmux control for handling miss spill miss. 2021-05-04 11:05:01 -05:00
Thomas Fleming
192878b124 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 03:14:38 -04:00
Thomas Fleming
dac07e34cf Fix bug in PMP checker 
Now we only enforce PMP regions if at least one is non-null
 2021-05-04 03:14:07 -04:00
ushakya22
da352c81e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
66344f0604 Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Thomas Fleming
d7fa0903bc Disable PMP checker to fix test loops 
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
 2021-05-04 01:56:05 -04:00
Domenico Ottolia
2c39c0a6a5 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
7c2481bea6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
4db3780ebb Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
39135f221e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
1556cc5b9f Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
Domenico Ottolia
84911e6345 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00