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190 Commits

Author SHA1 Message Date
Kunlin Han
22b59138f0 Remove all #delay from non-testbench. 2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912 Remove all #delay from non-testbench. 2024-03-13 10:31:40 -07:00
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
Rose Thompson
bd06a5ff88 Rough draft removal of duplicate BPBTAWrongE logic. 2024-02-01 16:57:33 -06:00
David Harris
f37c7bb1f6 Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this 2024-01-30 06:27:18 -08:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
dfe5ef4427 Added logic for the non-cache atomics. 2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185 Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit. 2024-01-15 17:36:01 -06:00
Jordan Carlin
092d10a3cd correct c.sext.b encoding and remove unreachable code in 01100 case 2024-01-12 19:09:10 -08:00
Rose Thompson
a932bf6b66 Removed unnecessary spill for compressed aligned to end of cache line or uncached access. 2024-01-10 13:06:16 -06:00
Rose Thompson
588e1caeba Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries. 2024-01-06 22:29:16 -06:00
David Harris
6181639003 Named IFU decomp generate block 2024-01-01 07:37:40 -08:00
Rose Thompson
6a787981c2 Restored cache store delay hazard. 2023-12-29 16:10:27 -06:00
Rose Thompson
f59fa5089d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-29 15:13:18 -06:00
Rose Thompson
8030b7d100 Added partial code for uncached amo operations. 
Minor fix for Makefile so coverage tests build.
 2023-12-29 15:07:20 -06:00
Rose Thompson
482529394a Fixed some of the uncached ifu bugs. 2023-12-29 09:53:22 -06:00
David Harris
e8df856fdb Renamed CMOp to CMOpM in mmu and cache 2023-12-25 05:57:41 -08:00
David Harris
06ddccd983 Fixed typo in IFU 2023-12-20 20:22:17 -08:00
David Harris
8eace30f49 Moved UnalignedPCNextF mux into IFU 2023-12-20 16:18:31 -08:00
Rose Thompson
9f4c32d49c Merge branch 'main' of github.com:ross144/cvw 2023-12-13 20:32:59 -06:00
David Harris
6c017141c5 Renamed HADE to ADUE for Svadu 2023-12-13 11:49:04 -08:00
Rose Thompson
3d0f9ce4f3 Cleaned up comments about pc reset. 2023-12-13 13:06:33 -06:00
Rose Thompson
c98c0dd3e0 Removed unnecessary pc reset logic from ifu and btb. 2023-12-13 13:05:10 -06:00
Rose Thompson
13bb5d845b On the way to solving the store delay hazard. 2023-12-13 10:39:01 -06:00
Rose Thompson
195def5808 Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero. 2023-11-27 21:24:30 -06:00
Rose Thompson
beb95dd592 Modified the pmachecker to correctly check the permissions for cmo instructions. 
However this isn't fully tested.
 2023-11-27 17:44:11 -06:00
David Harris
d3ce683e06 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
f89fd8a7fe removed unused cache signals 2023-11-20 23:16:35 -08:00
David Harris
8cb433cb66 Commented IROM preloading 2023-11-19 19:33:57 -08:00
David Harris
1f2899de14 Modified rams to take USE_SRAM rather than P to facilitate synthesis 2023-11-03 05:44:13 -07:00
David Harris
dd072c80f2 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
David Harris
402538e13c Temporary fix of InstrM to prevent testbench hanging 2023-11-03 04:59:44 -07:00
David Harris
09aebbf252 Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
David Harris
680fb3f30b Conditionally instantiate hardware in ifu 2023-10-30 20:55:00 -07:00
David Harris
afabc52b61 Gated InstrOrigM and PCMReg when not needed 2023-10-30 20:05:37 -07:00
David Harris
90a178e31e Made 2-bit AdrReg conditional on being needed 2023-10-30 19:13:43 -07:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
734bf021d7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
David Harris
3bb7539429 Fixed warnings of signed conversion and for Design Compiler 2023-10-24 14:01:43 -07:00
Rose Thompson
694ec18934 Added support for branch counters when there is no branch predictor. 2023-10-23 15:32:03 -05:00
Rose Thompson
1611d5ec3c Fixed issue 250. instruction classification was not correct for jalr ra (non zero). 2023-10-23 15:30:43 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
David Harris
19a6bbb01b UpdateDA cleanup: don't assert UpdateDA when there is no SVADU 2023-10-04 09:57:13 -07:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
Ross Thompson
f863cbf366 Actually fixed non-power of 2 issue with RAS. 
Added RAS swapping to branch predictor scripts and configurations.
 2023-09-27 12:25:05 -05:00
Ross Thompson
aeacb481aa Fixed sutble RAS bug when the stack size was not a power of 2. 2023-09-27 12:00:47 -05:00
David Harris
8f12c6f9a1 initial spill logic improvement 2023-09-03 04:21:13 -07:00
David Harris
bd6eef2a51 Initial implementation of SVNAPOT and SVPBMT does not break regression 2023-08-25 18:33:08 -07:00
Ross Thompson
0eac74ac7b Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7 Cache cleanup. 2023-07-31 14:12:53 -05:00