David Harris
28752303be
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
David Harris
8f12c6f9a1
initial spill logic improvement
2023-09-03 04:21:13 -07:00
David Harris
bd6eef2a51
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
Ross Thompson
0eac74ac7b
Initial CMO implementation. Just adds control signals into the L1 caches.
2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7
Cache cleanup.
2023-07-31 14:12:53 -05:00
Ross Thompson
d04d2afed2
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
009d8966e9
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
Ross Thompson
b8a243827b
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Harshini Srinath
a5561c2cf6
Update ifu.sv
...
Program clean up
2023-06-12 12:38:52 -07:00
Ross Thompson
1315a0bf4a
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Ross Thompson
fcb1c63f5f
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
Ross Thompson
052bc95966
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Ross Thompson
b91b54589e
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
2023-05-24 14:05:44 -05:00
Limnanthes Serafini
034c289a36
Misc typo and indent fixing.
2023-04-13 16:54:15 -07:00
David Harris
7ad05d9a42
Removed redundant stall signal to get spill coverage
2023-04-06 14:07:50 -07:00
Ross Thompson
366a96a0fc
Possible fix for issue 148.
...
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
e03a533775
Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault
2023-03-22 06:29:30 -07:00
David Harris
a1eccf37dc
Fix Issue 145
2023-03-22 04:33:14 -07:00
Ross Thompson
3cae6ca90f
Updated NextAdr to NextSet.
2023-03-13 14:54:13 -05:00
Ross Thompson
a5523400ae
Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
2023-03-12 13:21:22 -05:00
Ross Thompson
a6b851a672
Renamed signals to be consistent with textbook.
2023-03-06 18:29:31 -06:00
Ross Thompson
31fcc0daf7
Renamed PCFSpill to PCSpillF.
2023-03-06 17:50:57 -06:00
Ross Thompson
0cb5369351
Renamed BTB misprediction to BTA.
2023-03-03 00:18:34 -06:00
Ross Thompson
aabb454d1c
Added the i and d cache cycle counters.
2023-03-02 23:54:56 -06:00
Ross Thompson
b98e007a53
Cleaned up branch predictor performance counters.
2023-03-01 17:05:42 -06:00
Ross Thompson
a6917d07f3
Name cleanup.
2023-02-28 17:48:58 -06:00
Ross Thompson
2ebe600f54
Name changes to reflect diagrams.
2023-02-28 15:37:25 -06:00
Ross Thompson
bc5aecf948
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-27 09:48:03 -06:00
Ross Thompson
318189e5e6
Signal name changes.
2023-02-27 00:39:19 -06:00
David Harris
21b28fd1bb
Renamed DAPageFault to UpdateDA
2023-02-26 17:51:45 -08:00
Ross Thompson
8bd4a4c35b
Renamed signals to match new figures.
2023-02-24 19:51:47 -06:00
David Harris
f0566173e6
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-02-21 09:58:18 -08:00
David Harris
a445e53e8d
Fixed Issue #106 : fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.
2023-02-21 09:32:17 -08:00
Ross Thompson
545af7697f
Simiplified BTB.
2023-02-20 15:39:42 -06:00
Ross Thompson
6fbca64eb7
Experimental branch prediction optimization.
2023-02-10 15:45:56 -06:00
Ross Thompson
ca0eb5a591
Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic.
2023-02-10 10:33:10 -06:00
David Harris
6b9ae4fc89
Fixed merge issues on synthDC PR
2023-02-04 04:13:40 -08:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
