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556 Commits

Author SHA1 Message Date
Ross Thompson
fe72264de3 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
3ef2031791 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00
eroom1966
d61ed17730 Update for new layout of ImperasDV files 2023-06-12 09:29:07 +01:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
James E. Stine
842f51dfeb Add notes for FP SoftFloat/TestFloat build as may be vague for some 2023-06-11 15:14:02 -05:00
David Harris
c9ca5108b1 Merge pull request #312 from ross144/main 
Fixed typo in coremark makefile.
 2023-06-06 05:44:22 -07:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
Ross Thompson
76fd76c155 Oups forgot to include updates to the lint script itself. 2023-05-31 11:00:38 -05:00
David Harris
df57ccd885 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:53:28 -07:00
Ross Thompson
8648d0c25c Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
David Harris
51d001889a Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:40:56 -07:00
Ross Thompson
09aa460ed8 Updated do files for parameterization. 2023-05-30 15:38:03 -05:00
David Harris
fc1c4b710c Exclusions for decoders with new parameterization 2023-05-30 01:04:39 -07:00
David Harris
cc157463d5 Eliminated merging non-existent coverage 2023-05-30 00:38:30 -07:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
b91b54589e Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down. 2023-05-24 14:05:44 -05:00
Ross Thompson
88cc473c68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
David Harris
59020e6ef6 Removed unnecessary imperas tests from coverage 2023-05-23 15:43:11 -07:00
David Harris
8b69400034 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-22 11:27:57 -07:00
David Harris
21569b0a3b Verilate start 2023-05-22 10:30:39 -07:00
Ross Thompson
664231c0da Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
Ross Thompson
429875e8db Repaired wave file. 2023-05-22 10:09:33 -05:00
Ross Thompson
bfd0d263ca Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-22 10:06:42 -05:00
Ross Thompson
ad3ecd35f0 Repaired wave file. 2023-05-22 09:50:34 -05:00
David Harris
7b0d1a7883 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
d545a2ec74 Partially working local history repair. 2023-05-11 14:56:26 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
David Harris
3d3b3a7432 Fixed IROM coverage issues in IFU 2023-05-01 08:32:52 -07:00
David Harris
d5b718be38 IMMU exclude non word-sized accesses 2023-05-01 08:14:19 -07:00
David Harris
6253c042b2 Merged coverage exclusions for PMP 2023-04-28 08:04:25 -07:00
David Harris
194b848fbf PMA Checker coverage 2023-04-28 07:53:59 -07:00
Liam
4d8eafd27d Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
David Harris
a0e473b2e6 Merge pull request #282 from ross144/main 
Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag
 2023-04-27 07:23:10 -07:00
David Harris
ea3e3a1469 Merge pull request #283 from SydRiley/main 
Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
 2023-04-26 15:40:01 -07:00
Sydeny
6415a5f0b2 For ifu and lsu exclusions added missing row numbers 2023-04-26 15:30:22 -07:00
Ross Thompson
212fee3613 Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data. 2023-04-26 17:29:57 -05:00
Sydeny
f49acd1293 Exclusion in the ifu and lsu to increase coverage, added missing row numbers 2023-04-26 15:26:39 -07:00
Sydeny
1a04ffcca9 Excluding untoggled signals in ifu and lsu, ifu coverage from 83.68% to 84.06% and lsu from 93.45% to 93.58% 2023-04-26 14:37:55 -07:00
Sydeny
cda71bea3f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-26 03:00:25 -07:00
Sydeny
e5b3172cc9 added comments to exclusions 2023-04-26 03:00:13 -07:00
Alec Vercruysse
5612f30029 Cacheway Exclude FlushStage=1 when SetValidWay=1 
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).

My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
 2023-04-25 20:30:46 -07:00
Alec Vercruysse
c19ed1990f extend invalidatecache d$ exclusion to statement coverage 2023-04-25 17:00:13 -07:00
Diego Herrera Vicioso
d29dc30288 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
David Harris
086556310c Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
Ross Thompson
faac8d439a Merge pull request #264 from davidharrishmc/dev 
Added -fp flag to run arch64d/f tests in coverage
 2023-04-20 09:26:16 -05:00
David Harris
3a8d2db194 Merge pull request #262 from SydRiley/main 
removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
 2023-04-19 14:49:50 -07:00
Sydeny
ec730a7230 clarifying comments in exclusions 2023-04-19 14:47:34 -07:00
Sydeny
a132ffa7f7 removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% 2023-04-19 13:30:12 -07:00
David Harris
ea9639435e Added -fp flag to run arch64d/f tests in coverage 2023-04-19 13:07:07 -07:00
Alec Vercruysse
de93bd6937 D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
9ef85c547b fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
Sydeny
40853f4dc7 increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 2023-04-17 14:19:48 -07:00
David Harris
64fe318cb0 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Ross Thompson
30e3d2cdce Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
David Harris
48de682ea8 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
21db7a0d68 fdivsqrtfsm coverage attempt to waive a state 2023-04-13 17:40:14 -07:00
David Harris
5066cd99ab Merge pull request #237 from SydRiley/main 
fctrl coverage at 100% after removing redundancies from conditionals
 2023-04-13 17:10:46 -07:00
Limnanthes Serafini
1d72e56fec Merge branch 'openhwgroup:main' into cachesim 2023-04-13 16:54:35 -07:00
Limnanthes Serafini
95586abe09 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Sydeny
2b8891cefd Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Alec Vercruysse
680aee7e07 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
ad0e366766 track GetLinenum.do (tcl procedure to find line numbers to exclude) 2023-04-12 15:58:38 -07:00
Alec Vercruysse
01f2417524 cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
James E. Stine
001a364d6c Modification to testfloat.do to accept argument for nowave or by default none 2023-04-12 14:49:40 -05:00
Ross Thompson
10be07857c Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
1cb6e1751b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
Limnanthes Serafini
3f9a22e8d4 Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
e6cb928ab2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
095f3d5542 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
4cbb9bcec6 refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
James Stine
744e170be3 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
Limnanthes Serafini
e6a9d236b5 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
David Harris
a34867d14e Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic. ImperasDV is happy with these privileged tests now 2023-04-10 07:05:06 -07:00
eroom1966
dc79710724 add support into configuration for Zb(a,b,c,s) 2023-04-06 16:30:14 +01:00
eroom1966
adafc8037d add support for Sstc 2023-04-04 17:20:00 +01:00
David Harris
a6117e9bef Updated imperas.ic to enable B extension 2023-04-03 17:55:30 -07:00
David Harris
c1ec1cb09c Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests 2023-03-31 10:54:03 -07:00
David Harris
60a8a26f2e regression cleanup; unable to run buildroot coverage because of different config file 2023-03-31 09:59:38 -07:00
David Harris
69805b4a60 Regression update 2023-03-31 09:15:15 -07:00
David Harris
fd0c9e973d Coverage improvements in ieu, hazard units 2023-03-31 08:33:46 -07:00
Alec Vercruysse
a7066a20f1 add tests/coverage/ tests as a target to sim/Makefile 2023-03-27 14:02:30 -07:00
David Harris
a0504fd70c Commented out setting RISCV in run-imperas-linux.sh 2023-03-27 06:34:45 -07:00
eroom1966
1a10e48ecf update to allow running of ImperasDV with linux boot 
optimize performance of the tracer
 2023-03-27 09:46:16 +01:00
Lee Moore
4bb7dadc00 Merge branch 'openhwgroup:main' into add-linux 2023-03-27 09:44:13 +01:00
David Harris
2dda311df8 Avoid printing junk when running regression 2023-03-24 08:11:15 -07:00
David Harris
b674ebf7f4 100% IEU coverage 2023-03-23 17:25:27 -07:00
David Harris
121d1cea62 Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
David Harris
f4b252522e Coverage improvements 2023-03-23 09:06:05 -07:00
David Harris
ba4e0d2721 Merged bit manip 2023-03-23 06:55:29 -07:00
Kevin Kim
16a7236ac8 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 15:38:11 -07:00
James Stine
a4e5abad22 Change order of coverage and all in sim directory - order causing issue with compilation process of regression tests 2023-03-22 16:23:27 -05:00
Kip Macsai-Goren
8ef5422f67 fixed sim-wally-batch 2023-03-22 14:16:07 -07:00
Kip Macsai-Goren
03472ec7bb restored sim-wally-batch to existing tests 2023-03-22 13:32:24 -07:00
David Harris
3b3aa942c7 Added coverage tests to regression coverage 2023-03-22 13:00:10 -07:00
Kevin Kim
1eb96e2221 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 10:33:15 -07:00
eroom1966
259fbc8d77 support linux 2023-03-22 17:10:32 +00:00
David Harris
f6bc499f34 Testbench improvements for coverage reporting and running Imperas suite to raise test coverage 2023-03-22 04:34:49 -07:00
Kevin Kim
3f46dff23e Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
David Harris
95df66c5da Removed toggle coverage and generate recursive coverage report 2023-03-21 06:58:23 -07:00
Kevin Kim
4ecfa1bad3 added bitmanip 64 tests to updated regression script 
+ alu structural mux changes
 2023-03-20 14:19:39 -07:00
Kevin Kim
82d52f892b Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
David Harris
85fc86729b Renamed coverage-exclusions-rv64gc 2023-03-19 10:26:09 -07:00
David Harris
adbdc44f7b Improved coverage reporting 2023-03-19 10:24:35 -07:00
Mike Thompson
59985ff8a2 Merge pull request #139 from ross144/main 
Updates for book
 2023-03-14 15:44:59 -04:00
eroom1966
9ddfe52c9f Fix MISA RO and UART addresses 
It appears on inspection that the MISA register is read only in Wally
In which case this has now also been set in the ImperasDV representation
Also the Addresss for the UART R/W privileges are corrected
 2023-03-13 11:07:19 +00:00
Ross Thompson
a5523400ae Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
David Harris
1d2c8e1da3 Fixes to wally-batch for coverage 2023-03-10 13:33:32 -08:00
David Harris
005ca9650b Fixed crash with wrong number of arguments for coverage in regression-wally 2023-03-10 13:10:28 -08:00
David Harris
f411803bc4 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-10 12:47:30 -08:00
eroom1966
0233130d9c Enhancements to support the PMA ranges 2023-03-10 14:09:22 +00:00
David Harris
e3751e3a26 Modified regression and wally-batch.do to support -coverage 2023-03-09 15:59:57 -08:00
Kevin Kim
2111e06195 Merge branch 'openhwgroup:main' into bit-manip 2023-03-09 12:45:41 -08:00
Ross Thompson
68b437ce92 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-09 13:29:38 -06:00
Ross Thompson
4db17cde2f Updated testbench to record coremark performance counters. 
Added comment about mtval probably not being correct for compressed instructions.
 2023-03-08 17:11:27 -06:00
David Harris
3bd599d440 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-08 10:37:28 -08:00
eroom1966
39ac3cd18f Add support for setting PMP registers 
Add support for async DV
 2023-03-08 12:44:53 +00:00
David Harris
88c3a61cd7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-07 14:49:23 -08:00
Kip Macsai-Goren
f28a284e5e Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-07 13:45:04 -08:00
David Harris
77ba71be71 editorconfig to specify tabs/spaces. Fixed some tabs. Turn off coverage to speed up simulation 2023-03-07 06:31:40 -08:00
Ross Thompson
7b1b65e860 Working batch mode branch prediction simulations. 2023-03-04 17:59:16 -06:00
Ross Thompson
6766ecc28e Mostly working bpred launch script. 2023-03-04 17:20:45 -06:00
Ross Thompson
e9fa234410 Partial automation of branch predictor embenching. 2023-03-04 17:10:58 -06:00
Kip Macsai-Goren
4cede344a1 Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-04 14:43:12 -08:00
Ross Thompson
a3a45f696f Fixed a bunch of odd bugs with the test bench preventing correct measurement of performance counters. 2023-03-03 17:49:44 -06:00
Ross Thompson
b0a9499f86 Oups included the wave file in the wally-batch.do script. 2023-03-03 15:10:07 -06:00
Ross Thompson
486148b45d Fixed batch mode regression test to work with hpmc loggic. 
Added logic to exclude the embench warmups from preformance counters.
 2023-03-03 14:59:20 -06:00
Ross Thompson
0ecd1ef681 Setup the testbench to exclude the warmup from performance counter reports. 2023-03-03 13:10:01 -06:00
Kip Macsai-Goren
6be322941d Merge remote-tracking branch 'upstream/main' into bit-manip 2023-03-03 09:36:44 -08:00
Ross Thompson
dc49c2612d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-03 00:22:27 -06:00
eroom1966
fe4d9d3e37 fix the memory map privileges in the REF model view 2023-03-02 15:25:27 +00:00
Ross Thompson
b98e007a53 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
eroom1966
f86a12f282 update testbench for memory privileges 
also update configuration to define value of mimpid
 2023-03-01 15:37:11 +00:00
Kip Macsai-Goren
6b047065ef added bit manipulation tests to regression 2023-02-22 20:18:05 -08:00
Kip Macsai-Goren
ba3bfdf68b Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
cc47bd8bea Merge remote-tracking branch 'upstream/main' into main 2023-02-22 15:47:54 -08:00
eroom1966
dcfa153100 add support for idv package 2023-02-22 13:27:01 +00:00
Kip Macsai-Goren
d668c563f4 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
Ross Thompson
7df3a84060 Renamed branch predictors and consolidated global and gshare predictors. 2023-02-20 18:42:37 -06:00
Ross Thompson
1a46c1efb2 reset branch predictor after each test. 2023-02-19 23:48:37 -06:00
Ross Thompson
0f98cfe5b4 Simplified branch predictor. 2023-02-19 22:49:48 -06:00
Jacob Pease
45b264fa59 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
eroom1966
237a115377 add files to support coverage 2023-02-15 11:13:50 +00:00
Kip Macsai-Goren
76593cb282 Added necessary files to make bit make and run bit manipulation tests as part of regression 2023-02-10 10:35:19 -08:00
Ross Thompson
0678f3f2b7 Branch predictor cleanup. 2023-02-07 14:01:59 -06:00
Ross Thompson
70e96a7531 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-06 16:35:20 -06:00
Ross Thompson
d1cdbdd8df Merge branch 'main' of github.com:ross144/cvw 2023-02-06 16:34:28 -06:00
eroom1966
d88b56eebc remove leading space 2023-02-06 14:01:05 +00:00
eroom1966
232bfbcfd0 remerge changes 2023-02-06 13:43:12 +00:00
Ross Thompson
4fed1d5e3d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-04 11:28:26 -06:00
David Harris
ae54860805 Renamed wally-piplined.do to wally.do 2023-02-04 04:38:41 -08:00
David Harris
97ee3732fe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
80f42a8638 Renamed regression to sim 2023-02-02 14:48:23 -08:00