eroom1966 9ddfe52c9f Fix MISA RO and UART addresses ... It appears on inspection that the MISA register is read only in Wally In which case this has now also been set in the ImperasDV representation Also the Addresss for the UART R/W privileges are corrected		2023-03-13 11:07:19 +00:00
..
slack-notifier
wave-dos
bpred-sim.py
buildrootBugFinder.py	Renamed wally-piplined.do to wally.do	2023-02-04 04:38:41 -08:00
fpga-wave.do
imperas.ic	Fix MISA RO and UART addresses	2023-03-13 11:07:19 +00:00
lint-wally	Renamed regression to sim	2023-02-02 14:48:23 -08:00
linux-wave.do
make-tests.sh
Makefile
makefile-memfile
regression-wally
run-imperasdv-tests.bash	Renamed wally-piplined.do to wally.do	2023-02-04 04:38:41 -08:00
sim-buildroot
sim-buildroot-batch
sim-imperas
sim-testfloat
sim-testfloat-batch	Renamed regression to sim	2023-02-02 14:48:23 -08:00
sim-wally
sim-wally-batch
test
testfloat.do
wally-batch.do	Fixes to wally-batch for coverage	2023-03-10 13:33:32 -08:00
wally-imperas-cov.do
wally-imperas-no-idv.do
wally-imperas.do
wally.do
wave-all.do
wave-fpu.do
wave.do