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2068 Commits

Author SHA1 Message Date
Ross Thompson
de7f3b14fc More branch predictor cleanup. 
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
 2023-01-13 12:57:18 -06:00
Ross Thompson
cf608ee45f Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
ea7c447218 Possible minor enhancement to gshare. 2023-01-13 12:32:39 -06:00
Ross Thompson
55169fa9b0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-13 10:26:07 -06:00
Ross Thompson
395b7a5b32 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
ef4c684336 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
9917be817c Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
a68773eba1 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
2e622c9860 Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
4733b787f8 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
3cc37e3f12 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
2f2f3d6da5 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
5ad0bacf5b Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
94f24d3f58 Added instruction logger. 2023-01-12 10:09:34 -06:00
David Harris
fdcb1f08ce Privileged unit formatting 2023-01-12 07:41:30 -08:00
David Harris
e58879f2d0 restructured code for lint error related to CORRSHIFTSZ 2023-01-12 07:34:37 -08:00
David Harris
93233fbb45 Restructured negateintres to avoid lint error, but one still shows on shiftcorrection 2023-01-12 07:28:52 -08:00
David Harris
1ad6ac1393 MDU comment cleanup 2023-01-12 07:15:14 -08:00
David Harris
768c1bc703 Header comments 2023-01-12 04:35:44 -08:00
Ross Thompson
b96a53df0a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-11 23:02:14 -06:00
Katherine Parry
77a982c977 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
David Harris
67d474995e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 19:48:37 -08:00
David Harris
bfd47ff7f5 Removed unused wallypipelinedsocwrapper 2023-01-11 19:48:34 -08:00
Ross Thompson
e0867b1840 Completed review of LSU. 2023-01-11 19:06:03 -06:00
Ross Thompson
aba1df9abf Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 18:52:49 -06:00
Ross Thompson
318ceba34d Improved LSU formating. 2023-01-11 18:52:46 -06:00
sarah-harris
796a189451 privilege unit -> privileged unit in ifu.sv 
privilege unit -> privileged unit in ifu.sv
 2023-01-11 16:33:08 -08:00
Ross Thompson
ad22a9ea02 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:26:11 -06:00
sarah-harris
203cc164d9 Added Sarah.Harris@unlv.edu to alu.sv 
Added Sarah.Harris@unlv.edu to alu.sv
 2023-01-11 15:20:41 -08:00
Ross Thompson
b60e9730a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:15:49 -06:00
David Harris
8c6ddcc15b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
Ross Thompson
bccef3b39c Updated header for LSU. 2023-01-11 17:15:07 -06:00
David Harris
9a057ef5cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 15:13:58 -08:00
Ross Thompson
a8931e0211 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:09:23 -06:00
Katherine Parry
4556839960 fixed typo bug in fpu 2023-01-11 17:07:02 -06:00
Ross Thompson
6999b4562e Updated branch predictor. 2023-01-11 17:00:45 -06:00
David Harris
3ea4dd4898 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
99ff78b902 FPU cleanup 2023-01-11 12:27:00 -08:00
David Harris
4ff2627a50 fpu cleanup 2023-01-11 12:18:06 -08:00
David Harris
d1bfdddd8c Rename FP and FPU to F in signal names 2023-01-11 11:46:36 -08:00
David Harris
15026f61f7 FPU comments 2023-01-11 11:31:28 -08:00
David Harris
654abcde61 Replaced MDUE with IntDivE in FDIVSQRT 2023-01-11 11:06:37 -08:00
Ross Thompson
1df9c5f13e Optimized gshare. 2023-01-10 18:12:48 -06:00
David Harris
f6987fab8c Switched to XZeroE from NumerZeroE in square root preprocessor 2023-01-10 12:37:49 -08:00
David Harris
739c2c8322 Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
446b5fa83f Division constant cleanup 2023-01-10 11:14:59 -08:00
David Harris
4a34007b49 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-09 13:04:37 -08:00
David Harris
b2ec52c94d Changed DIVN from NF+3 to NF+2, cleanup 2023-01-09 13:04:34 -08:00
Ross Thompson
f330d877ac Added folded gshare predictor with k=16 and depth=10. 2023-01-09 14:41:03 -06:00
David Harris
48f31d4b24 Divider constant cleanup, made CORRSHIFTSZ consistent 2023-01-09 12:34:19 -08:00
Ross Thompson
302a2e0116 Added better branch predictor to fpga config. 2023-01-09 13:46:30 -06:00
Ross Thompson
ca55bd8444 Fixed branch predictor. 2023-01-09 13:45:49 -06:00
Ross Thompson
6a616617d1 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
816006ac1b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-09 00:18:11 -06:00
Ross Thompson
6326e6984c Might have actually solved the gshare bug. 2023-01-09 00:11:25 -06:00
Ross Thompson
6cbce9672d Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3 core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
David Harris
d7e420e350 Cache code cleanup 2023-01-07 15:49:18 -08:00
David Harris
dc12291ee3 Cache code cleanup 2023-01-07 15:46:23 -08:00
David Harris
057183bcc9 Cache code cleanup 2023-01-07 15:44:44 -08:00
David Harris
0a25f18a07 Cache code cleanup 2023-01-07 15:42:08 -08:00
David Harris
0ad707f1a5 Cache code cleanup 2023-01-07 15:39:13 -08:00
Ross Thompson
bf08c57ab0 Added branch outcome logger to testbench 2023-01-07 13:16:57 -06:00
Ross Thompson
475becb414 Removed unused rv64BP config. 2023-01-07 12:17:40 -06:00
David Harris
f541a277a8 Remove unused CACHE_ENABLED parameter 2023-01-07 09:57:24 -08:00
David Harris
33c910f952 Remove unused signals 2023-01-07 06:26:29 -08:00
David Harris
dc526c92bd Removed unused signals 2023-01-07 06:06:54 -08:00
David Harris
01525399cc Removed unused signals; added check for atomic in pmachecker 2023-01-07 05:59:56 -08:00
David Harris
21b9f50851 Remove conditional from inside decompress module 2023-01-07 05:51:47 -08:00
David Harris
8506f120e1 Remove unused signals 2023-01-07 05:46:22 -08:00
David Harris
44352ced64 Branch logic simplification and remove unused signals 2023-01-07 05:42:34 -08:00
David Harris
d8f0425467 vclean working; started removing unused signals 2023-01-07 05:34:58 -08:00
David Harris
f4cb652a00 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-07 04:49:40 -08:00
David Harris
2188ff879b code cleanup 2023-01-07 04:49:25 -08:00
Ross Thompson
f119b492bb Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-06 15:18:13 -06:00
Ross Thompson
7223d1e05c Added python script to post process performance counter metrics. 2023-01-06 15:15:54 -06:00
Katherine Parry
1bcb1725f5 renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
David Harris
c260354817 Removed unused UARCH configuration entries 2023-01-06 05:11:14 -08:00
Ross Thompson
01d4e942d0 Added more missing files. 2023-01-06 00:12:08 -06:00
Ross Thompson
8a5916ce66 Addd missing file. 2023-01-06 00:09:18 -06:00
Ross Thompson
09bb733088 Added code to print out performance counters at end of each test. 2023-01-05 18:00:11 -06:00
Ross Thompson
78e441fb38 More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
65dd86b726 Keep around the old gshare. 2023-01-05 15:55:46 -06:00
Ross Thompson
2224679694 Added speculative gshare. 2023-01-05 14:18:00 -06:00
Ross Thompson
9d03109f34 Officially added global history with speculation to types of branch predictors. 2023-01-05 14:04:09 -06:00
Ross Thompson
0737efc86c More branch predictor cleanup. 2023-01-05 13:36:51 -06:00
Ross Thompson
808c106504 Two bit predictor cleanup. 2023-01-05 13:27:22 -06:00
Ross Thompson
14ebf2360d Simplified gshare. 2023-01-04 23:51:09 -06:00
Ross Thompson
0eceeeeeaa Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
davidharrishmc
4a2ed0142f
Update decompress.sv 
typo
 2023-01-04 17:01:26 -08:00
Katherine Parry
970318f881 forgot the normshift module 2023-01-04 10:48:19 -06:00
Katherine Parry
95a1ddd636 some commenting fixes, converter optimizations, and moves normshift into postproc 2023-01-03 15:55:30 -06:00
David Harris
43f45c62a6 Made Q4.k interface to fgen2/4 consistent 2023-01-01 15:06:32 -08:00
David Harris
3d5acc7c2a Simplified intdiv selection logic to muxes 2023-01-01 14:04:37 -08:00
David Harris
f8af51e07b Handle special case Int Div/Rem of |A| < |B| in a single cycle 2023-01-01 13:54:01 -08:00
David Harris
f567577ede Fixed radix 2 k = 1 lint 2022-12-31 07:01:50 -08:00
David Harris
c1689b54bb Fixed backward mux in fdivsqrtstage2 2022-12-31 06:55:20 -08:00
David Harris
7c7d40ad63 Broken commit starting to address radix 2 issues 2022-12-31 06:19:15 -08:00
David Harris
50af122909 Moved shared config so wally-shared only has values a user would alter 2022-12-31 05:51:42 -08:00
David Harris
3ac62c74c2 fdivsqrt post processing cleanup 2022-12-31 05:45:15 -08:00
David Harris
99b244c8c4 fdivsqrt post processing major simplification 2022-12-31 05:42:51 -08:00
David Harris
f587933fb5 fdivsqrt post processing simplification 2022-12-31 05:37:48 -08:00
David Harris
5edc925dff fdivsqrt post processing simplification 2022-12-31 05:36:09 -08:00
David Harris
6832b9d9f6 config file, comment, postproc cleanup 2022-12-31 05:20:56 -08:00
Cedar Turek
0836d4d4f0 removed unnecessary values from shared config. unbroke division 2022-12-30 21:26:55 -08:00
Cedar Turek
e994f26d6d simplified initU and UM logic, separated radix2/4 logic 2022-12-30 18:57:07 -08:00
Cedar Turek
fb9a0c797f various formatting fixes and comments 2022-12-30 18:41:40 -08:00
Cedar Turek
286e43807a added mux to intdiv result 2022-12-30 18:06:35 -08:00
Cedar Turek
ae447e42df removed unnecessary mdue gating 2022-12-30 17:53:06 -08:00
Cedar Turek
ba90d868db took out broken muxes 2022-12-30 15:13:52 -08:00
Cedar Turek
545a3ff363 various cleanup 2022-12-30 14:31:23 -08:00
Cedar Turek
3170130c94 Code cleanup 2022-12-30 14:13:33 -08:00
Ross Thompson
9d5213b71e Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-30 15:04:54 -06:00
Ross Thompson
a538d4316f Cleanup spill logic. 2022-12-30 14:59:51 -06:00
Ross Thompson
fdd7b68501 Signal renames for PC*NextF and SelSpillNextF. 2022-12-30 14:21:20 -06:00
Cedar Turek
158e23b5a5 commented complicated step/right shift calc 2022-12-30 12:03:10 -08:00
Cedar Turek
eef1d4dd66 comment cleaning 2022-12-30 11:11:34 -08:00
Cedar Turek
7e5cafeda3 Described internal signals of fdivsqrt top 2022-12-30 11:01:02 -08:00
Cedar Turek
8cb4a7a69a Commented fdivsqrt module 2022-12-30 10:52:25 -08:00
Ross Thompson
ed536dd142 Removed da page fault from spill logic. 2022-12-30 12:51:56 -06:00
Cedar Turek
3115df9380 Begin commenting divsqrt 2022-12-30 10:43:02 -08:00
Ross Thompson
80a135f101 Spill only occurs on 32-bit instructions. 2022-12-30 12:41:25 -06:00
Katherine Parry
aca6f0d4e6 removed ethe second bit from fma alignment shift 2022-12-30 12:07:44 -06:00
Ross Thompson
b1f68a1d85 Modified IROM to return the correct offset when unaligned. 2022-12-30 11:48:40 -06:00
Katherine Parry
5844a596a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-30 09:56:35 -06:00
David Harris
58218dbdd1 continued simplifying integer division special cases 2022-12-30 07:40:28 -08:00
David Harris
bd16fd79d4 started simplifying integer division special cases 2022-12-30 07:34:26 -08:00
David Harris
30dc45c764 removed duplicate quotient mux 2022-12-30 07:17:38 -08:00
David Harris
61230c967c simplified sign handling mux 2022-12-30 07:10:47 -08:00
David Harris
ba976d66e4 Radix 4 divsqrt 2022-12-30 07:01:44 -08:00
David Harris
3c475455d9 Clean up sqrt preproc 2022-12-30 07:00:48 -08:00
David Harris
4fb8396867 Clean up sqrt initialization mux 2022-12-30 06:55:20 -08:00
David Harris
dba3ffe767 Reduced size of preproc right shift 2022-12-30 06:47:40 -08:00
David Harris
0e9bd5dab5 fdivsqrtpreproc shift simplification 2022-12-30 06:45:51 -08:00
David Harris
e9b314f902 fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression 2022-12-30 06:40:25 -08:00
David Harris
ef37070eee Fixed register timing failure on SpecialCaseM in fdivsqrt 2022-12-29 21:09:23 -08:00
Ross Thompson
872ff619e3 Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
Ross Thompson
c725b5534a Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-29 17:07:53 -06:00
Ross Thompson
654b10894c Re-enabled the branch predictor in rv64gc. 2022-12-29 17:07:50 -06:00
Katherine Parry
90eb4fc1f1 minor optimizations and renaming 2022-12-29 15:54:17 -06:00
Katherine Parry
89e8df084a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-29 12:37:51 -06:00
David Harris
776f4714af Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
6664cb9db4 Factored out hardware unique to RV64 and to IDIV 2022-12-29 07:36:26 -08:00
Katherine Parry
1b4fa38510 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
Alessandro Maiuolo
7c19665dea added script in pipelined folder to run regressions with all radix/copies configurations 2022-12-28 07:32:35 -08:00
David Harris
7780b44973 fdivsqrtfsm conditional on IDIV (fixed typo) 2022-12-27 22:16:48 -08:00
David Harris
5ee44b7405 fdivsqrtfsm conditional on IDIV 2022-12-27 22:15:45 -08:00
David Harris
db933aa7e2 fdivsqrtfsm conditional on IDIV 2022-12-27 22:14:09 -08:00
Cedar Turek
ef360f0539 idiv passing radix 2, four copies 2022-12-27 22:11:18 -08:00
Cedar Turek
4ed2c6255c idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
David Harris
9964fc9ebe Moved IDIV in fdivsqrtfms into generate block 2022-12-27 22:04:50 -08:00
David Harris
a832605658 Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
David Harris
d59878a886 Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
Cedar Turek
a559abe554 Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. 2022-12-27 21:34:27 -08:00
David Harris
665b545fd0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-27 21:30:13 -08:00
David Harris
87abed6722 cleanup 2022-12-27 21:29:36 -08:00
David Harris
6cf73cdaee Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
David Harris
c08811357c Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
Ross Thompson
a129e27502 signal name changes in ram2p. 2022-12-27 15:07:01 -06:00
Ross Thompson
66b2fbd836 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-27 15:06:25 -06:00
Ross Thompson
3f4b3a4159 Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
David Harris
dfc0b5d1ad Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00
David Harris
4850d058b2 fdiv typo 2022-12-27 10:30:42 -08:00
David Harris
acc9498ae2 Made SqrtE only true on square root so gating with ~MDUE can be removed) 2022-12-27 10:27:07 -08:00
David Harris
e34b8139af Check for non-negative W in int sign handling 2022-12-27 06:35:17 -08:00
Cedar Turek
f48b7d7ef9 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
0b14aa852d fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
bebaf08bed took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
c326a274ac Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
2de66e9eef Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
a7204c9012 Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
David Harris
fb0b2d4227 Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
David Harris
7e77a39d32 Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
David Harris
d627512d2b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-25 20:12:55 -08:00
Ross Thompson
4f436dc7f0 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
David Harris
0cc2b0fcd2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-24 12:24:38 -08:00
Ross Thompson
0d6ce1d459 Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
David Harris
10af4e4353 ALU cleanup 2022-12-24 07:18:35 -08:00
cturek
cc6f219bdd Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
Ross Thompson
b0d6c9616e Minor optimizations. 2022-12-23 20:11:36 -06:00
Ross Thompson
6e9d1eb180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
4b50ffac91 reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
6f9e21d61b Improved comment. 2022-12-23 15:13:15 -06:00
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
fe9361de34 Removed XEnE, YEnE, and ZEnE from forward logic. 
Cleanup comments.
 2022-12-23 14:27:03 -06:00
Ross Thompson
af9afafdae Cleanup floating point hazard logic. 2022-12-23 14:21:47 -06:00
Ross Thompson
b4c7998ded DON'T USE. First commit in attempt to move fpustall detection into the decode stage. 2022-12-23 12:47:18 -06:00
Ross Thompson
f6f66cb79e Removed ZForwardEnE and replaced with ZEnE. 
Similar for YForwardEnE.
 2022-12-23 12:27:51 -06:00
Ross Thompson
ca67e5588d Removed unnecessary stall when MatchDE was driven 1 by RdE == 0. 2022-12-23 11:45:42 -06:00
David Harris
f038494760 Commented out fdiv early termination - broke fsqrt test 2022-12-23 00:58:55 -08:00
David Harris
e061bacc9d Fixed early termination on fdivsqrt 2022-12-23 00:53:55 -08:00
David Harris
0505f1fd37 Moved InstrValidNotFLushed to csr including InstrValidM 2022-12-23 00:27:44 -08:00
David Harris
3b1fe78bdc Removed unused StallW from CSRs 2022-12-23 00:21:36 -08:00
David Harris
9e21358d75 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
0a7ed944a5 Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
56312cd0a6 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
4d509f94ec FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
2d72bed1f4 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
Ross Thompson
98b824c4c4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-22 22:51:33 -06:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00