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https://github.com/openhwgroup/cvw
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Removed unused StallW from CSRs
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@ -199,7 +199,7 @@ module csr #(parameter
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// CSRs
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///////////////////////////////////////////
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csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW,
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csri csri(.clk, .reset, .InstrValidNotFlushedM,
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.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
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.MExtInt, .SExtInt, .MTimerInt, .MSwInt,
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.MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
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@ -219,7 +219,7 @@ module csr #(parameter
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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csrm csrm(.clk, .reset, .InstrValidNotFlushedM, .StallW,
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csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
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.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
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@ -227,7 +227,7 @@ module csr #(parameter
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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csrs csrs(.clk, .reset, .InstrValidNotFlushedM, .StallW,
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csrs csrs(.clk, .reset, .InstrValidNotFlushedM,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
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@ -235,7 +235,7 @@ module csr #(parameter
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.SCOUNTEREN_REGW,
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.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW,
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csru csru(.clk, .reset, .InstrValidNotFlushedM,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.IllegalCSRUAccessM);
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@ -38,7 +38,7 @@ module csri #(parameter
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SIP = 12'h144
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) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM, StallW,
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input logic InstrValidNotFlushedM,
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input logic CSRMWriteM, CSRSWriteM,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [11:0] CSRAdrM,
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@ -72,7 +72,7 @@ module csrm #(parameter
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MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
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) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM, StallW,
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input logic InstrValidNotFlushedM,
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input logic CSRMWriteM, MTrapM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
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@ -50,7 +50,7 @@ module csrs #(parameter
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) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM, StallW,
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input logic InstrValidNotFlushedM,
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input logic CSRSWriteM, STrapM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
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@ -37,7 +37,7 @@ module csru #(parameter
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FRM = 12'h002,
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FCSR = 12'h003) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM, StallW,
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input logic InstrValidNotFlushedM,
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input logic CSRUWriteM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] CSRWriteValM,
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