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Commented out fdiv early termination - broke fsqrt test
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@ -116,7 +116,7 @@ module fdivsqrtfsm(
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if (SpecialCaseE) state <= #1 DONE;
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else state <= #1 BUSY;
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end else if (state == BUSY) begin
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if (step == 1 | WZeroM) state <= #1 DONE; // finished steps or terminate early on zero residual
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if (step == 1 /*| WZeroM */) state <= #1 DONE; // finished steps or terminate early on zero residual
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step <= step - 1;
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end else if (state == DONE) begin
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if (StallM) state <= #1 DONE;
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