Header comments

pipelined/src/fpu/fclassify.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Floating-point classify unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fcmp.sv

@@ -7,6 +7,8 @@
 //
 // Purpose: Floating-point comparison unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fctrl.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: floating-point control unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fcvt.sv

@@ -7,6 +7,8 @@
 //
 // Purpose: Floating point conversions of configurable size
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // Int component of the Wally configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Exponent caclulation for divide and square root
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 2 F Addend Generator
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 4 F Addend Generator
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: divsqrt state machine for multi-cycle operations
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: k stages of divsqrt logic, plus registers
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Divide/Square root postprocessing
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 2 Quotient Digit Selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 4 Quotient Digit Selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Comparator-based Radix 4 Quotient Digit Selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
+// Purpose: radix-2 divsqrt recurrence stage
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
+// Purpose: radix-4 divsqrt recurrence stage
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 2 unified on-the-fly converter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 4 unified on-the-fly converter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fhazard.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Determine forwarding, stalls and flushes for the FPU
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fma/fma.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Floating point multiply-accumulate of configurable size
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fma/fmaadd.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: FMA significand adder
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fma/fmaalign.sv

@@ -7,6 +7,8 @@
 //
 // Purpose: FMA alginment shift
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fma/fmaexpadd.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: FMA exponent addition
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fma/fmalza.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Leading Zero Anticipator
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fma/fmamult.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: FMA Significand Multiplier
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fma/fmasign.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: FMA Sign Logic
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fpu.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Floating Point Unit Top-Level Interface
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fregfile.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: 3R1W 4-port register file for FPU
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/fsgninj.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: FPU Sign Injection instructions
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/cvtshiftcalc.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Conversion shift calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/divshiftcalc.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Division shift calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/flags.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Post-Processing flag calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/fmashiftcalc.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: FMA shift calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/negateintres.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Negate integer result
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/normshift.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: normalization shifter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/postprocess.sv

@@ -4,8 +4,10 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Post-Processing
+// Purpose: Post-Processing: normalization, rounding, sign, flags, special cases
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/resultsign.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: calculating the result's sign
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/round.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Rounder
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/roundsign.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Sign calculation for rounding
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/shiftcorrection.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: shift correction
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/postproc/specialcase.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: special case selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/unpack.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: unpack X, Y, Z floating-point inputs
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/fpu/unpackinput.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: unpack input: extract sign, exponent, significand, characteristics
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/generic/flop/flop.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// ordinary flip-flop
 module flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopen.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable
 module flopen #(parameter WIDTH = 8) (
   input  logic             clk, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopenl.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable and synchronous load
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous load
 module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   input  logic clk, load, en,
   input  TYPE d,

pipelined/src/generic/flop/flopenr.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous reset
 module flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopenrc.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous reset, enabled clear
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous reset, enabled clear
 module flopenrc #(parameter WIDTH = 8) (
   input  logic             clk, reset, clear, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopens.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous set
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous set
 module flopens #(parameter WIDTH = 8) (
   input  logic             clk, set, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopr.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with synchronous reset
 module flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/floprc.sv

@@ -4,8 +4,8 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
-// 
+// Purpose: D flip-flop with synchronous reset and clear
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with synchronous reset, synchronous clear
 module floprc #(parameter WIDTH = 8) (
   input  logic clk,
   input  logic reset,

pipelined/src/generic/flop/synchronizer.sv

@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// ordinary flip-flop
 module synchronizer ( 
   input  logic clk,
   input  logic d, 

pipelined/src/ieu/comparator.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Branch comparison
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/ieu/controller.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Top level controller module
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/ieu/datapath.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Wally Integer Datapath
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/ieu/extend.sv

@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: 
+// Purpose: Produce sign-extended immediates from various formats
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/ieu/forward.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Determine datapath forwarding
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.2.2.3)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/ieu/ieu.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: Integer Execution Unit: datapath and controller
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/ieu/regfile.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: 3-port register file
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/ieu/shifter.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: RISC-V 32/64 bit shifter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/privileged/csrm.sv

@@ -7,7 +7,10 @@
 //
 // Purpose: Machine-Mode Control and Status Registers
 //          See RISC-V Privileged Mode Specification 20190608 
-// 
+// Note: the CSRs do not support the following optional features
+//   - Disabling portions of the instruction set with bits of the MISA register
+//   - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/wally/wallypipelinedsoc.sv

@@ -4,12 +4,7 @@
 // Written: David_Harris@hmc.edu 6 November 2020
 // Modified: 
 //
-// Purpose: System on chip including pipelined processor and memories
-// Full RV32/64IC instruction set
-//
-// Note: the CSRs do not support the following features
-//- Disabling portions of the instruction set with bits of the MISA register
-//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
+// Purpose: System on chip including pipelined processor and uncore memories/peripherals
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -32,35 +27,36 @@
 `include "wally-config.vh"
 
 module wallypipelinedsoc (
-  input  logic 		   clk, reset_ext, 
-  output logic       reset,
+  input  logic 		            clk, 
+  input  logic                reset_ext, 
+  output logic                reset,
   // AHB Interface
-  input  logic [`AHBW-1:0]  HRDATAEXT,
-  input  logic 		   HREADYEXT, HRESPEXT,
-  output logic 		   HSELEXT,
+  input  logic [`AHBW-1:0]    HRDATAEXT,
+  input  logic 		            HREADYEXT, HRESPEXT,
+  output logic 		            HSELEXT,
   // outputs to external memory, shared with uncore memory
-  output logic 		   HCLK, HRESETn,
+  output logic 		            HCLK, HRESETn,
   output logic [`PA_BITS-1:0] HADDR,
-  output logic [`AHBW-1:0] HWDATA,
-  output logic [`XLEN/8-1:0] HWSTRB,
-  output logic 		   HWRITE,
-  output logic [2:0] 	   HSIZE,
-  output logic [2:0] 	   HBURST,
-  output logic [3:0] 	   HPROT,
-  output logic [1:0] 	   HTRANS,
-  output logic 		   HMASTLOCK,
-  output logic 		   HREADY,
+  output logic [`AHBW-1:0]    HWDATA,
+  output logic [`XLEN/8-1:0]  HWSTRB,
+  output logic 		            HWRITE,
+  output logic [2:0] 	        HSIZE,
+  output logic [2:0] 	        HBURST,
+  output logic [3:0] 	        HPROT,
+  output logic [1:0] 	        HTRANS,
+  output logic 		            HMASTLOCK,
+  output logic 		            HREADY,
   // I/O Interface
-  input  logic       TIMECLK,
-  input logic [31:0] 	   GPIOPinsIn,
-  output logic [31:0] 	   GPIOPinsOut, GPIOPinsEn,
-  input logic 		   UARTSin,
-  output logic 		   UARTSout,
-  input logic 		   SDCCmdIn,
-  output logic 		   SDCCmdOut,
-  output logic 		   SDCCmdOE,			  
-  input logic [3:0] 	   SDCDatIn,
-  output logic 		   SDCCLK			  
+  input  logic                TIMECLK,
+  input  logic [31:0] 	        GPIOPinsIn,
+  output logic [31:0] 	      GPIOPinsOut, GPIOPinsEn,
+  input  logic 		            UARTSin,
+  output logic 		            UARTSout,
+  input  logic 		            SDCCmdIn,
+  output logic 		            SDCCmdOut,
+  output logic 		            SDCCmdOE,			  
+  input  logic [3:0] 	        SDCDatIn,
+  output logic 		            SDCCLK			  
 );
 
   // Uncore signals