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https://github.com/openhwgroup/cvw
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reworked negitive sticky bit handeling in fma
This commit is contained in:
Katherine Parry
parent
f038494760
commit
4b50ffac91
@ -9,7 +9,6 @@ add wave -noupdate /testbenchfp/Res
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add wave -noupdate /testbenchfp/Ans
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add wave -noupdate /testbenchfp/DivStart
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add wave -noupdate /testbenchfp/FDivBusyE
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add wave -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/state
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add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
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add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
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add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*
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@ -20,22 +19,5 @@ add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/*
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add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/*
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add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/*
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add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/*
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WC
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WS
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#add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WCA
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#add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WSA
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/U
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UM
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UNext
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/UMNext
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/otfc/otfc2/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/stage/fdivsqrtstage/qsel/qsel2/*
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# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/fdivsqrtstage/stage/genblk1/qsel4/*
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/*
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/expcalc/*
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add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/*
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add wave -group {Sqrt} -noupdate -recursive /testbenchfp/fdivsqrt/fdivsqrt/*
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add wave -group {Testbench} -noupdate /testbenchfp/*
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add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*
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@ -46,7 +46,9 @@ module fmaadd(
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output logic [3*`NF+5:0] Sm // the positive sum
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);
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logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum
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logic [3*`NF+5:0] PreSumdebug, NegPreSumdebug; // possibly negitive sum
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logic NegSum; // was the sum negitive
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logic NegSumdebug; // was the sum negitive
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///////////////////////////////////////////////////////////////////////////////
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// Addition
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@ -58,12 +60,13 @@ module fmaadd(
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assign PmKilled = KillProd ? '0 : Pm;
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// Do the addition
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// - calculate a positive and negitive sum in parallel
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// Zsticky Psticky
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// PreSum -1 = don't add 1 +1 = add 2
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// NegPreSum +1 = add 2 -1 = don't add 1
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// for NegPreSum the product is set to -1 whenever the product is killed, therefore add 1, 2 or 0
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assign {NegSum, PreSum} = {{`NF+3{1'b0}}, PmKilled, 1'b0, InvA&ZmSticky&KillProd} + {InvA, AmInv} + {{3*`NF+6{1'b0}}, InvA&~((ZmSticky&~KillProd))};
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assign NegPreSum = Am + {{`NF+2{1'b1}}, ~PmKilled, 2'b11} + {(3*`NF+4)'(0), ZmSticky&~KillProd, ~(ZmSticky)};
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// if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum
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// prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation
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// ie ~(InvA&ZmSticky&~KillProd)&InvA = (~ZmSticky|KillProd)&InvA
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// addend - prod where product is killed (and not exactly zero) then don't add +1 from negation
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// ie ~(InvA&ZmSticky&KillProd)&InvA = (~ZmSticky|~KillProd)&InvA
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assign {NegSum, PreSum} = {{`NF+3{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*`NF+6{1'b0}}, (~ZmSticky|KillProd)&InvA};
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assign NegPreSum = Am + {{`NF+2{1'b1}}, ~PmKilled, 2'b0} + {(3*`NF+3)'(0), (~ZmSticky|~KillProd)&InvA, 2'b0};
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum : PreSum;
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@ -55,11 +55,10 @@ module fmaalign(
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// This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
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assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+3) - {2'b0, Ze};
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// Defualt Addition without shifting
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// Defualt Addition with only inital left shift
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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// the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...)
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assign ZmPreshifted = {Zm,(3*`NF+5)'(0)};
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assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
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@ -77,7 +76,7 @@ module fmaalign(
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ZmSticky = ~(XZero|YZero);
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// If the addend is too small to effect the addition
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// - The addend has to shift two past the end of the addend to be considered too small
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// - The addend has to shift two past the end of the product to be considered too small
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// - The 2 extra bits are needed for rounding
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// | 54'b0 | 106'b(product) | 2'b0 |
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@ -689,8 +689,8 @@ module testbenchfp;
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.Xe(Xe), .Ye(Ye), .Ze(Ze),
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.Xm(Xm), .Ym(Ym), .Zm(Zm),
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.XZero, .YZero, .ZZero, .Ss, .Se,
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.OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .SCnt, .As, .Ps,
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.Pe, .ZmSticky, .KillProd);
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.OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .InvA, .SCnt, .As, .Ps,
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.ZmSticky);
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end
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postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
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@ -700,8 +700,8 @@ module testbenchfp;
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.XZero(XZero), .YZero(YZero), .ZZero(ZZero), .CvtShiftAmt(CvtShiftAmtE),
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.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
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.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
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.FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se),
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.FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
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.FmaZmS(ZmSticky), .FmaSe(Se),
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.FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
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.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
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if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
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