Merge branch 'main' of github.com:davidharrishmc/riscv-wally

pipelined/src/cache/cache.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Storage for data and meta data.
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/cache/cacheLRU.sv

@@ -6,7 +6,7 @@
 //          Tested for Powers of 2.
 //
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/cache/cachefsm.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Controller for the dcache fsm
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/cache/cacheway.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/cache/subcachelineread.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Controller for the dcache fsm
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ebu/ahbcacheinterface.sv

@@ -10,7 +10,7 @@
 // This register should be necessary for timing.  There is no register in the uncore or
 // ahblite controller between the memories and this cache.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ebu/ahbinterface.sv

@@ -10,7 +10,7 @@
 // This register should be necessary for timing.  There is no register in the uncore or
 // ahblite controller between the memories and this cache.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ebu/amoalu.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Performs AMO operations
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ebu/buscachefsm.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Load/Store Unit's interface to BUS for cacheless system
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ebu/busfsm.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Load/Store Unit's interface to BUS for cacheless system
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ebu/controllerinputstage.sv

@@ -12,7 +12,7 @@
 //          Bus width presently matches XLEN
 //          Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ebu/ebu.sv

@@ -12,7 +12,7 @@
 //          Bus width presently matches XLEN
 //          Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fclassify.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point classify unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fcmp.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Floating-point comparison unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fctrl.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: floating-point control unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 F Addend Generator
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 4 F Addend Generator
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 Quotient Digit Selection
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 4 Quotient Digit Selection
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Comparator-based Radix 4 Quotient Digit Selection
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 unified on-the-fly converter
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 4 unified on-the-fly converter
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fhazard.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Determine forwarding, stalls and flushes for the FPU
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fma/fma.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating point multiply-accumulate of configurable size
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fma/fmaadd.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA significand adder
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fma/fmaalign.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: FMA alginment shift
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fma/fmaexpadd.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA exponent addition
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fma/fmalza.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Leading Zero Anticipator
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fma/fmamult.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA Significand Multiplier
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fma/fmasign.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA Sign Logic
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fpu.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating Point Unit Top-Level Interface
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fregfile.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: 3R1W 4-port register file for FPU
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/fsgninj.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FPU Sign Injection instructions
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/cvtshiftcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Conversion shift calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/divshiftcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Division shift calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/flags.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Post-Processing flag calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/fmashiftcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA shift calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/negateintres.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Negate integer result
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/normshift.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: normalization shifter
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/postprocess.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Post-Processing
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/resultsign.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: calculating the result's sign
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/round.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Rounder
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/roundsign.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Sign calculation ofr rounding
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/shiftcorrection.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: shift correction
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/postproc/specialcase.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: special case selection
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/unpack.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: unpack X, Y, Z floating-point inputs
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/fpu/unpackinput.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: unpack input: extract sign, exponent, significand, characteristics
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/adder.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Adder
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/aplusbeq0.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Determine if A+B = 0.  Used in FP divider.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/arrs.sv

@@ -9,7 +9,7 @@
 //          arrs takes in the asynchronous reset and outputs an asynchronous
 //          rising edge, but then syncs the falling edge to the posedge clk.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/binencoder.sv

@@ -5,7 +5,7 @@
 //
 // Purpose: one-hot to binary encoding.
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/clockgater.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Clock gater model. Must use standard cell for synthesis.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/counter.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Counter with reset and enable
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/csa.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: 3:2 carry-save adder
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/decoder.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Binary encoding to one-hot decoder
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flop.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flopen.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flopenl.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flopenr.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flopenrc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flopens.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flopr.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/floprc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: various flavors of flip-flops
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/synchronizer.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Two-stage flip-flop synchronizer
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/lzc.sv

@@ -5,7 +5,7 @@
 //
 // Purpose: Leading Zero Counter
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/mem/ram1p1rwbe.sv

@@ -9,7 +9,7 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/mem/ram2p1r1wb.sv

@@ -16,7 +16,7 @@
 // example
 // mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/mem/ram2p1rwbefix.sv

@@ -9,7 +9,7 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/mem/rom1p1r.sv

@@ -5,7 +5,7 @@
 //
 // Purpose: Single-ported ROM
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/mux.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Various flavors of multiplexers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/neg.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: 2's complement negator
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/onehotdecoder.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Bin to one hot decoder. Power of 2 only.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/or_rows.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Various flavors of multiplexers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/priorityonehot.sv

@@ -16,7 +16,7 @@
 //        in  01011101010100000
 //        out 00000000000100000
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/prioritythermometer.sv

@@ -12,7 +12,7 @@
 //        in  01011101010100000
 //        out 00000000000011111
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/hazard/hazard.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Determine forwarding, stalls and flushes
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/alu.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: RISC-V Arithmetic/Logic Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/comparator.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Branch comparison
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/controller.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Top level controller module
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/datapath.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Wally Integer Datapath
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/extend.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: 
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/forward.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Determine datapath forwarding
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/ieu.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Integer Execution Unit: datapath and controller
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/regfile.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: 3-port register file
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ieu/shifter.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: RISC-V 32/64 bit shifter
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ifu/BTBPredictor.sv

@@ -9,7 +9,7 @@
 // Purpose: BTB model.  Outputs type of instruction (currently 1 hot encoded. Probably want 
 // to encode to reduce storage), valid, target PC.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ifu/RAsPredictor.sv

@@ -8,7 +8,7 @@
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ifu/bpred.sv

@@ -9,7 +9,7 @@
 // Purpose: Branch prediction unit
 //          Produces a branch prediction based on branch history.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ifu/decompress.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Expand 16-bit compressed instructions to 32 bits
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ifu/foldedgshare.sv

@@ -8,7 +8,7 @@
 //
 // Purpose: Global History Branch predictor with parameterized global history register
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ifu/globalHistoryPredictor.sv

@@ -8,7 +8,7 @@
 //
 // Purpose: Global History Branch predictor with parameterized global history register
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/ifu/globalhistory.sv

@@ -8,7 +8,7 @@
 //
 // Purpose: Global History Branch predictor with parameterized global history register
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //