161 Commits

Author	SHA1	Message	Date
Ross Thompson	3fb0a13fe2	Moved other SRAMs to generic/mem.	2022-09-21 12:36:03 -05:00
Ross Thompson	ac864a6ca3	Merged together bram1p1rw with sram1p1rw as sram1p1rw. ... Fixed a major issue with the real SRAM implemenation.	2022-09-21 12:20:00 -05:00
Ross Thompson	c0884ecc63	Modified sram1p1rw to support 3 different implementation styles. ... SRAM, Read first, and Write first.	2022-09-21 11:26:00 -05:00
Ross Thompson	2c86badeb2	pipelining of fetch into evict AHB requests.	2022-09-13 17:51:55 -05:00
Ross Thompson	7f1ae039b0	Optimization. Able to remove hptw address muxes from the E stage.	2022-09-08 15:51:18 -05:00
Ross Thompson	1b339f0547	Moved files around.	2022-08-31 14:08:06 -05:00
Ross Thompson	8156109add	More cleanup.	2022-08-31 11:12:38 -05:00
Ross Thompson	4b167ad21e	More simplifications.	2022-08-31 10:45:16 -05:00
Ross Thompson	a93c5b0f0a	Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier.	2022-08-31 10:36:30 -05:00
Ross Thompson	ed2a9225ea	Removed unused old versions of the bus controllers.	2022-08-31 09:51:54 -05:00
Ross Thompson	89f13370e2	Removed old signals.	2022-08-31 09:50:39 -05:00
Ross Thompson	5409501ca6	Maybe fixed it?	2022-08-30 18:08:34 -05:00
Ross Thompson	8b9f30c91a	more progress.	2022-08-30 17:32:32 -05:00
Ross Thompson	315f662eb9	More progress.	2022-08-30 15:27:19 -05:00
Ross Thompson	637d60b64c	Progress.	2022-08-30 14:17:00 -05:00
Ross Thompson	8cf3c7b352	new cache bus fsm not working but lints. ... Forgot a few files in the last commit.	2022-08-30 10:58:07 -05:00
David Harris	5f37e16b62	Fixed rv32e LSU and IFU issues	2022-08-25 20:02:38 -07:00
David Harris	bc0c7d0cd8	Cleaned up SelBusWord	2022-08-25 11:18:13 -07:00
David Harris	3ba961d1a8	renamed BusBuffer to FetchBuffer	2022-08-25 10:44:39 -07:00
Ross Thompson	701324eeb8	Updated ila signals. ... Improve fpga wave config. added back in the fpga preload.	2022-08-25 09:03:29 -05:00
Ross Thompson	ebe4339953	Updated fpga test bench. ... Solved read delay cache bug. Introduced during cache optimizations.	2022-08-21 15:59:54 -05:00
Ross Thompson	85dbec5969	Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.	2022-08-21 15:28:29 -05:00
Ross Thompson	2ba390adf4	Possible reduction of ignorerequest.	2022-08-19 18:07:44 -05:00
Ross Thompson	517c0f6c35	Changed signal names.	2022-08-17 16:12:04 -05:00
Ross Thompson	f6e5746e59	Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.	2022-08-17 16:09:20 -05:00
Ross Thompson	413a9bf58b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
Ross Thompson	57fcf0ef79	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
Ross Thompson	3cd8404917	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
Katherine Parry	1bd6351e1f	re-added FStore2 in Cache	2022-07-29 22:54:49 +00:00
Ross Thompson	40e7cda84a	Don't use this commit yet. Untested.	2022-07-24 15:40:52 -05:00
Ross Thompson	719b00e338	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	cd68896637	Merged evict dirty clear with flush write back.	2022-07-24 00:22:43 -05:00
Ross Thompson	05484c4c05	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	17ae1a1b1b	cache fsm cleanup after removal of replay.	2022-07-22 23:25:09 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Ross Thompson	1cad05fef9	Minor cleanup of cache.	2022-07-19 23:04:23 -05:00
Ross Thompson	8698799077	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Ross Thompson	a79e5e11f6	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Ross Thompson	0ef6137ab9	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
Ross Thompson	8356e5d742	Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.	2022-07-17 16:20:04 -05:00
Katherine Parry	18d7fee541	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
David Harris	03a20610aa	added comment about checking SRAM size	2022-07-10 12:48:51 +00:00
David Harris	d1a7832dd9	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
Katherine Parry	62205ebb3b	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
Katherine Parry	97e7e619d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
James Stine	99fed5d59f	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
David Harris	38ef8eebbb	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	425fec0f41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00