naichewa
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4651b807ed
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added test cases
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2023-11-02 15:43:08 -07:00 |
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naichewa
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9aa8a7af3e
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comments, more test cases
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2023-11-01 01:26:34 -07:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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Rose Thompson
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0fd5b3b2ce
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Updated comments in the cboz tests.
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2023-10-20 15:15:47 -05:00 |
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Rose Thompson
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5a4028064a
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Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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6245748ed7
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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
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434d6b2c5c
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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naichewa
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aa5abfc8e8
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always working after reg bit swizzle changes
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2023-10-13 14:22:32 -07:00 |
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naichewa
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f231c3d3a3
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correct delay0, fmt register test entries
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2023-10-12 15:13:23 -07:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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Ross Thompson
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12c3c98824
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Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
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2023-08-30 11:29:44 -05:00 |
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David Harris
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8d3ff59673
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Completed basic tests of svnapot and svpbmt
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2023-08-28 06:57:35 -07:00 |
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Ross Thompson
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914b6f9734
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Now have CBOZ instructions working!
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2023-08-24 16:47:35 -05:00 |
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Ross Thompson
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310b700550
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Have a working 32 bit cbom test!
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2023-08-21 13:46:09 -05:00 |
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Ross Thompson
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d4c6ba627d
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Working CBO tests for 64 bit!
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2023-08-21 12:55:07 -05:00 |
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Ross Thompson
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5ed096e4bc
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Made a bunch of progress towards getting cbo instructions tested.
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2023-08-21 11:46:21 -05:00 |
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David Harris
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c137a1c8cf
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Fixed timer interrupt testing
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2023-06-09 17:20:41 -07:00 |
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David Harris
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f68b9c224a
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Fixed WALLY-trap test case to use menvcfg
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2023-06-09 15:24:26 -07:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
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David Harris
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19096a812a
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Added Zifencei ISA to tests where necessary to support new compiler
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2023-05-16 11:18:27 -07:00 |
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David Harris
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0a7a159d69
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Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
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2023-05-14 06:58:29 -07:00 |
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Kip Macsai-Goren
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34200e8c76
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restored original virt mem tests when svadu is not supported
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2023-04-11 18:47:08 -07:00 |
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Kip Macsai-Goren
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c4766c8a02
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renamed virt mem tests to include svadu
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2023-04-11 18:46:37 -07:00 |
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Kip Macsai-Goren
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b2d6084eea
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removed unnecessary 'deadbeef's at the end of reference outputs
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2023-04-11 18:32:04 -07:00 |
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Kip Macsai-Goren
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a82c0a7780
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Modified virt mem tests to do correct r/w when svadu is enabled
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2023-04-11 18:08:30 -07:00 |
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Kip Macsai-Goren
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e0b938b409
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Removed Trap outputs from writes covered by SVADU
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2023-04-11 17:41:57 -07:00 |
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Kip Macsai-Goren
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a899606c2b
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Removed Sail from virt mem tests due to sail not recognizing SVADU
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2023-04-11 17:41:31 -07:00 |
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Kip Macsai-Goren
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19305fe60a
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Added sail simulation to priv tests that support it
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2023-04-11 13:26:59 -07:00 |
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Kip Macsai-Goren
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2e151b6b08
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updated tests to reflect non-writeable bits of deleg
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2023-03-29 15:24:00 -07:00 |
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David Harris
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2e5c50e24a
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Fixed RV32 tests after PMP fix
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2023-03-28 08:35:23 -07:00 |
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David Harris
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e8904411ce
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Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
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2023-03-28 06:58:17 -07:00 |
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Kip Macsai-Goren
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106ed02a7e
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Revert "added premilinary boundary ccrossing cases"
This reverts commit 7870148814.
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2023-03-24 11:27:41 -07:00 |
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Kip Macsai-Goren
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ff59fefcc9
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replaced inerrupt tests with allowed versions
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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6f15ae1225
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Added cause_s_soft_from_m_interrupt
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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7870148814
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added premilinary boundary ccrossing cases
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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db6caedfec
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added in the CSR name for stimecmp(h)
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2023-03-04 15:53:03 -08:00 |
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Kip Macsai-Goren
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ab6b953a4b
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removed changes to counteren from stimecmp tests
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2023-03-04 15:46:57 -08:00 |
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Kip Macsai-Goren
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ac5c53a870
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Added correct causing and handling of S time interrupts to test suite.
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2023-03-04 15:04:17 -08:00 |
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David Harris
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f0c0111ab0
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Renamed section 12.3 to 8.3 in MMU test definitions
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2023-02-19 05:46:46 -08:00 |
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Kip Macsai-Goren
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ee1bcf62ee
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Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
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2023-01-28 17:29:35 -08:00 |
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Kip Macsai-Goren
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964084f0b3
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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d25d699800
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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a37bde7452
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updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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David Harris
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ca949f2110
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Only delegated bits of SIP are readable
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2022-12-21 12:32:49 -08:00 |
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Ross Thompson
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f6393d1288
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Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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