Ross Thompson
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42e6364b3d
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Merge branch 'main' of github.com:ross144/cvw
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2023-07-17 15:52:27 -05:00 |
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Ross Thompson
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c82638774f
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Updated the FPGA zero stage bootloader.
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2023-07-17 15:52:13 -05:00 |
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Ross Thompson
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50bc679fef
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Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.
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2023-07-14 16:31:44 -05:00 |
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David Harris
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644afa16cd
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Clean up privilege rs1 decoding and implement svinval as sfence.vma
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2023-07-13 02:41:17 -07:00 |
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Ross Thompson
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625192d9a4
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Merge branch 'main' of github.com:ross144/cvw into main
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2023-07-11 15:08:26 -05:00 |
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Ross Thompson
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38f32805ae
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Created separate temporary testbench for xcelium.
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2023-07-11 15:07:33 -05:00 |
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Ross Thompson
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4c4eb080ee
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RTL changes for Xcelium.
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2023-07-11 10:51:02 -05:00 |
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Ross Thompson
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12beada55b
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Fixed the privilege decoder bug which prevented the fpga linux boot.
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2023-07-10 17:00:06 -05:00 |
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Ross Thompson
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beaec570c7
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Merge pull request #359 from davidharrishmc/dev
CSR updates
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2023-07-10 13:16:57 -04:00 |
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David Harris
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e713ba8d3e
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MENVCFG only exists if U_SUPPORTED
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2023-07-09 18:25:07 -07:00 |
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Ross Thompson
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27f6f00402
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Changes for xcelium.
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2023-07-07 18:22:28 -05:00 |
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Ross Thompson
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cdf73d3b51
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Updated comments.
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2023-07-06 15:24:26 -05:00 |
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Ross Thompson
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e4555dc4af
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Removed unused parameter.
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2023-07-06 14:57:07 -05:00 |
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Ross Thompson
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2ce8b66574
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-07-06 14:55:43 -05:00 |
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David Harris
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369e8fb5ec
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Removed outdated commment about endianness
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2023-07-06 12:41:46 -07:00 |
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David Harris
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869a7cb827
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Removed MTINST, which is not used in a system without a hypervisor
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2023-07-06 12:40:53 -07:00 |
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Ross Thompson
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a963e50e88
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It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga.
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2023-07-06 14:07:37 -05:00 |
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Ross Thompson
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df56ff73c0
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This is at least functionally correct, but has verilator lint issues.
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2023-07-06 11:53:34 -05:00 |
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Ross Thompson
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c000366d3e
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closer, but the wally32/64priv tests are failing.
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2023-07-05 17:47:38 -05:00 |
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Ross Thompson
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98147e116a
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Partially solved fpga boot.
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2023-07-05 17:30:55 -05:00 |
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David Harris
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269bb688ea
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Fixed comment typo
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2023-07-04 11:34:58 -07:00 |
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David Harris
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410ef01627
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fixed spacing in fdivsqrt
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2023-07-04 11:27:36 -07:00 |
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David Harris
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afe66d0ee4
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Added prefetch instructions; sent cbo instructions to LSU
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2023-07-02 10:55:35 -07:00 |
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David Harris
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723b8266cb
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Added prefetch signals
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2023-07-02 10:06:58 -07:00 |
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David Harris
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482e4e6e92
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Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions
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2023-07-02 09:35:05 -07:00 |
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David Harris
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c48283801a
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Fixed csr typos
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2023-07-02 02:01:40 -07:00 |
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David Harris
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61208e486c
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Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode
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2023-07-02 02:00:27 -07:00 |
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David Harris
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b6ae5661b4
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Added environment configuration control (menvcfg/senvcfg) of cbo instructions
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2023-07-02 01:52:25 -07:00 |
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David Harris
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15314a9c9a
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Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
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2023-07-02 00:34:30 -07:00 |
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David Harris
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41e9f20943
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improved decoder checking atomic and RW and MW and privileged instructions
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2023-07-02 00:02:03 -07:00 |
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David Harris
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e34ef4d636
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improved decoder checking atomic instructions
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2023-07-01 23:10:57 -07:00 |
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David Harris
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d930be332e
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Improved instruction decoding for illegal floating-point loads/stores and fences
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2023-07-01 22:48:04 -07:00 |
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Ross Thompson
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f5cee3fb66
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-18 16:37:19 -05:00 |
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David Harris
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c383407d5c
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Removed redundant and not-covered atomic check from StoreStallD
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2023-06-16 16:05:53 -07:00 |
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Ross Thompson
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c44d4321fb
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FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
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2023-06-16 15:40:13 -05:00 |
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Ross Thompson
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bdc5656ef3
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Added comment to uart LCR to check reset value after updating FPGA.
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2023-06-15 15:39:51 -05:00 |
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Ross Thompson
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4428babda9
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 15:38:38 -05:00 |
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Ross Thompson
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85567841eb
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Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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Ross Thompson
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d2219023c3
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 14:57:23 -05:00 |
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David Harris
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3ca271b6a7
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Added input gating on FPU
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2023-06-15 12:38:33 -07:00 |
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David Harris
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9e839988dc
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Gated MDU to save power; doesn't seem to have affected simulation time
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2023-06-15 12:17:23 -07:00 |
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David Harris
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9f88848832
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Bit manipulation comment cleanup
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2023-06-15 12:16:46 -07:00 |
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Ross Thompson
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75b5c23edd
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Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
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2023-06-15 14:05:44 -05:00 |
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David Harris
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a62211bad1
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Gated inputs to BMU when inactive to save power and simulation time
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2023-06-15 11:56:59 -07:00 |
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Ross Thompson
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009d8966e9
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Got the srams parameterized correctly now.
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2023-06-15 13:42:24 -05:00 |
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David Harris
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d3aebc00d4
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Fixed UART merge conflict
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2023-06-15 11:36:37 -07:00 |
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Ross Thompson
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b8a243827b
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Found a whole bunch of files still using the old `define configurations.
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2023-06-15 13:09:07 -05:00 |
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Harshini Srinath
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dd7c13cc2d
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Update wallypipelinedsoc.sv
Program clean up
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2023-06-15 10:39:37 -07:00 |
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Harshini Srinath
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b4469fd3bf
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Update wallypipelinedcore.sv
Program clean up
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2023-06-15 10:38:38 -07:00 |
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Harshini Srinath
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85a513e542
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Update cvw.sv
Program clean up
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2023-06-15 10:29:33 -07:00 |
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