Rose Thompson
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88745e27d3
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Fixed ila after updates.
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2024-11-13 12:57:02 -06:00 |
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Rose Thompson
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827f986fae
|
This configuration of the vcu108 actually seems to work.
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2024-11-05 16:01:08 -06:00 |
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Rose Thompson
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aaf36d11b5
|
Now have the vcu108 kind of working with the new spi controller. However, it still has issues mounting the ext4 partition.
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2024-11-05 15:20:53 -06:00 |
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Rose Thompson
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57d1709582
|
The path to the zsbl was wrong all this time, but for reason was working with older versions of Ubuntu, but one 24.04 it causes vivado to not find the rom and ram.
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2024-10-30 16:01:11 -05:00 |
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Rose Thompson
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261e503061
|
Updates for arty A7 device tree.
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2024-09-05 12:02:07 -07:00 |
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Rose Thompson
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3a0e28fea0
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Added missing spi debugger.
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2024-09-02 14:47:31 -07:00 |
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Rose Thompson
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869860bc55
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Merge branch 'main' of github.com:ross144/cvw
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2024-09-02 14:08:48 -07:00 |
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Jacob Pease
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4b8d35bd8a
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-30 14:18:54 -05:00 |
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Jacob Pease
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4acac08320
|
Fixed Arty constraints and corrected typos.
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2024-08-30 14:17:37 -05:00 |
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Rose Thompson
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f1d9e18dee
|
Modified fpga config to support two fpga boards with different amount of memory.
Modified vcu108 constraints to better constrain the spi clock and in/out.
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2024-08-29 16:12:58 -07:00 |
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Rose Thompson
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7e16ddd859
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Improved fpga synth script.
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2024-08-27 15:50:05 -07:00 |
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Rose Thompson
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f20a1564fa
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Added SPI debugger.
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2024-08-26 17:22:13 -07:00 |
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Rose Thompson
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ee1e09a6a2
|
VCU108 now boot linux at 50MHz!
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2024-08-23 17:18:47 -07:00 |
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Rose Thompson
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14083bc642
|
VCU108 is not synthesizing at 50MHz. Still running into a few problems
with the new SPI sd card device.
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2024-08-23 16:17:15 -07:00 |
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Rose Thompson
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842aea157c
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Updated vc108 constraints for spi based sd card and setting 50 Mhz.
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2024-08-23 15:59:11 -07:00 |
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Rose Thompson
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b471913d9f
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On the way to making vcu108 work again.
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2024-08-23 14:45:22 -07:00 |
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Rose Thompson
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fc80bf1251
|
More updates to fpga IP module names.
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2024-08-22 14:31:39 -07:00 |
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Jacob Pease
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d8b75440b6
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With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
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2024-08-20 16:24:37 -05:00 |
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Jacob Pease
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af2344d2d5
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Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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2024-08-06 17:09:39 -05:00 |
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Jacob Pease
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665396fdb3
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SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.
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2024-08-06 16:57:57 -05:00 |
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Jacob Pease
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11a057b0b3
|
Updated wally source files for zsbl testing.
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2024-08-02 15:33:57 -05:00 |
|
Jacob Pease
|
0dae881a0d
|
Fixed SDCCLK name discrepency.
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2024-07-24 22:48:31 -05:00 |
|
Rose Thompson
|
8ca565ed53
|
Updated for a better ILA rvvi debugger.
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2024-07-22 17:44:04 -05:00 |
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Rose Thompson
|
121342f4cc
|
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
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2024-07-22 16:12:06 -05:00 |
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Jacob Pease
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cec39fd3aa
|
Added new SDC clock constraint.
|
2024-07-22 13:05:16 -05:00 |
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Rose Thompson
|
24609f0b7f
|
Now have configurations to switch between supporting RVVI over ethernet.
|
2024-07-22 10:51:13 -05:00 |
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Rose Thompson
|
00840e4893
|
Made the fpga top level configurable between rvvi synth and not.
|
2024-07-19 17:35:30 -05:00 |
|
Rose Thompson
|
0d40b8c933
|
Cleanup in prep to merge the rvvi branch into main.
|
2024-07-19 15:48:20 -05:00 |
|
Ross Thompson
|
f0096f5a43
|
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
|
2024-07-10 15:10:37 -05:00 |
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Ross Thompson
|
e6dc962d11
|
Yay! the trigger is correctly working now!
|
2024-07-10 12:05:10 -05:00 |
|
Ross Thompson
|
ccf4bb8ddc
|
Maybe have the incircuit trigger working.
|
2024-06-26 16:15:46 -07:00 |
|
Ross Thompson
|
612a281f62
|
Added module to receive ethernet frame and trigger the ila.
|
2024-06-26 11:05:31 -07:00 |
|
Ross Thompson
|
563980443a
|
Merge branch 'main' into rvvi
|
2024-06-10 18:10:23 -07:00 |
|
Rose Thompson
|
6a4c8667df
|
Added new signals to ILA to debug the RVVI tracer.
The tracer appears to be stuck and the CPU is never getting out of (into reset).
|
2024-05-30 16:43:25 -05:00 |
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Jacob Pease
|
7ecd1c7d5f
|
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
|
2024-05-30 15:48:27 -05:00 |
|
Rose Thompson
|
9703055758
|
The FPGA is synthesizing with the rvvi and ethernet hardware.
|
2024-05-30 15:37:17 -05:00 |
|
Rose Thompson
|
26cd22c388
|
Replaced fpga's verilog top with system verilog.
|
2023-12-15 13:42:52 -06:00 |
|
Rose Thompson
|
34631c54d3
|
Get's the fpga building again after the git history rewrite.
|
2023-12-14 17:08:25 -06:00 |
|
Rose Thompson
|
cdd21d6635
|
Added menvcfg to debugger for checking what linux has configured.
|
2023-11-19 13:44:22 -06:00 |
|
Ross Thompson
|
055e00b8ac
|
Pushed vcu118 to 71MHz.
|
2023-08-25 17:04:50 -05:00 |
|
Jacob Pease
|
2bf6207919
|
Added help option to the flash-sd script.
|
2023-08-22 13:37:33 -05:00 |
|
Ross Thompson
|
a16cde3dc6
|
Removed unused file.
|
2023-08-21 15:12:59 -05:00 |
|
Ross Thompson
|
1e0f1aeeac
|
Updated artyA7 debugger to match book.
|
2023-08-21 14:35:42 -05:00 |
|
Ross Thompson
|
fb1c1a1832
|
Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
|
2023-08-02 16:14:04 -05:00 |
|
Ross Thompson
|
5790dafdce
|
Fixed constraint in VCU118.
|
2023-08-02 13:02:28 -05:00 |
|
Ross Thompson
|
c4ae856f92
|
Clean up vcu118 synth scripts.
|
2023-08-01 14:39:33 -05:00 |
|
Ross Thompson
|
06efd2cdde
|
Pushed performance of arty a7 to 23Mhz.
|
2023-07-31 14:13:09 -05:00 |
|
Ross Thompson
|
49b87d4550
|
Merge branch 'main' of github.com:ross144/cvw
|
2023-07-24 10:47:05 -05:00 |
|
Ross Thompson
|
065e5e98c9
|
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
|
2023-07-24 10:46:49 -05:00 |
|
Ross Thompson
|
ab6ef5bb58
|
At least it simulates and gets through fpga elaboration.
|
2023-07-21 18:40:26 -05:00 |
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