165 Commits

Author	SHA1	Message	Date
Ross Thompson	3625fc3bed	Patched the ILA's debug2.xdc constraint file to work with the wally memory design.	2022-01-06 15:18:18 -06:00
Ross Thompson	c19b910f6e	Updated fpga ILA constraints to match the new changes to the rtl.	2022-01-06 11:56:09 -06:00
Ross Thompson	1ab3a17ff7	Updates to support fpga.	2022-01-05 18:07:23 -06:00
Ross Thompson	53736096a6	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-20 10:03:19 -06:00
Ross Thompson	0257c08641	Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.	2021-12-19 14:00:30 -06:00
Ross Thompson	79ec4161b6	Added more debugging code for FPGA.	2021-12-17 14:40:25 -06:00
Ross Thompson	54767822ec	Reverted 23Mhz to 10Mhz. The flash card can't work at that speed. ... added icache debugging signals.	2021-12-15 10:24:29 -06:00
Ross Thompson	f061a26411	Cleaned up fpga synthesis script.	2021-12-13 18:26:54 -06:00
Ross Thompson	bb79f70a63	Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.	2021-12-12 17:21:44 -06:00
Ross Thompson	e6f2a316c8	Missed constraints file for xilinx ILA.	2021-12-12 15:06:29 -06:00
Ross Thompson	517cae796c	Fixed more constraint issues in fpga. ... Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim.	2021-12-05 15:14:18 -06:00
Ross Thompson	cb744280c3	Fixed a bunch of fpga issues.	2021-12-03 17:47:54 -06:00
Ross Thompson	5d4051d1c2	Constraints for fpga are still wrong.	2021-12-02 14:23:21 -06:00
Ross Thompson	2a7467c76d	Separated timing constraints from ILA.	2021-12-01 18:15:04 -06:00
Ross Thompson	6a228ade04	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00