Rose Thompson 261e503061 Updates for arty A7 device tree.		2024-09-05 12:02:07 -07:00
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artyddr3.ucf
constraints-ArtyA7.xdc	Fixed Arty constraints and corrected typos.	2024-08-30 14:17:37 -05:00
constraints-vcu108.xdc	Modified fpga config to support two fpga boards with different amount of memory.	2024-08-29 16:12:58 -07:00
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc
marked_debug_all.txt
marked_debug_rvvi.txt	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
marked_debug_small.txt
marked_debug_spi.txt	Updates for arty A7 device tree.	2024-09-05 12:02:07 -07:00
marked_debug.txt	Updates for arty A7 device tree.	2024-09-05 12:02:07 -07:00
small-debug-rvvi.xdc	Updated for a better ILA rvvi debugger.	2024-07-22 17:44:04 -05:00
small-debug-spi.xdc	Updates for arty A7 device tree.	2024-09-05 12:02:07 -07:00
small-debug.xdc
vcu-small-debug.xdc	VCU108 is not synthesizing at 50MHz. Still running into a few problems	2024-08-23 16:17:15 -07:00