cvw/fpga/constraints
Rose Thompson f1d9e18dee Modified fpga config to support two fpga boards with different amount of memory.
Modified vcu108 constraints to better constrain the spi clock and in/out.
2024-08-29 16:12:58 -07:00
..
artyddr3.ucf
constraints-ArtyA7.xdc
constraints-vcu108.xdc
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc
marked_debug_all.txt
marked_debug_rvvi.txt
marked_debug_small.txt
marked_debug.txt
small-debug-rvvi.xdc
small-debug.xdc
vcu-small-debug.xdc