Jacob Pease 4b8d35bd8a Merge branch 'main' of github.com:openhwgroup/cvw		2024-08-30 14:18:54 -05:00
..
artyddr3.ucf
constraints-ArtyA7.xdc	Fixed Arty constraints and corrected typos.	2024-08-30 14:17:37 -05:00
constraints-vcu108.xdc	Added SPI debugger.	2024-08-26 17:22:13 -07:00
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
marked_debug_all.txt	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
marked_debug_rvvi.txt	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
marked_debug_small.txt
marked_debug.txt	Improved fpga synth script.	2024-08-27 15:50:05 -07:00
small-debug-rvvi.xdc	Updated for a better ILA rvvi debugger.	2024-07-22 17:44:04 -05:00
small-debug.xdc	Now have configurations to switch between supporting RVVI over ethernet.	2024-07-22 10:51:13 -05:00
vcu-small-debug.xdc	VCU108 is not synthesizing at 50MHz. Still running into a few problems	2024-08-23 16:17:15 -07:00