cvw/fpga/constraints
2024-08-27 15:50:05 -07:00
..
artyddr3.ucf
constraints-ArtyA7.xdc
constraints-vcu108.xdc Added SPI debugger. 2024-08-26 17:22:13 -07:00
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc
marked_debug_all.txt
marked_debug_rvvi.txt
marked_debug_small.txt
marked_debug.txt Improved fpga synth script. 2024-08-27 15:50:05 -07:00
small-debug-rvvi.xdc
small-debug.xdc
vcu-small-debug.xdc VCU108 is not synthesizing at 50MHz. Still running into a few problems 2024-08-23 16:17:15 -07:00