Ross Thompson
27042f028e
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
Ross Thompson
c56c4db47f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
Skylar Litz
0c69d3291d
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Kip Macsai-Goren
53f392a62f
light cleanup
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
225b38e793
added high bit registers to CSR permission tests
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
6c1383e2a0
added CSR permission and minfor to 32 bit tests
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
5df0a9531f
merged test macros in with 32 bit tests
2022-02-15 20:19:14 +00:00
David Harris
aa990be959
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
David Harris
126f196d46
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-15 19:01:42 +00:00
David Harris
93fa34f9f0
Sythesis uncertainty cleanup
2022-02-15 19:01:38 +00:00
Kip Macsai-Goren
9266bc382e
light cleanup for privileged tests
2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
856ef6b85a
updated tests to use the combined library
2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
9a05ee3308
Began to merge test-lib and test-macros into one file
2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
b90477495c
updated verify to only use comments with "#"
2022-02-15 17:06:16 +00:00
Ross Thompson
fcbb577f31
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
143eb0ae65
srt fixes
2022-02-14 18:40:27 +00:00
David Harris
3598e05998
srt batch files
2022-02-14 18:37:46 +00:00
ushakya22
3e2e9bc6a0
bring branch back into main
...
Merge branch 'srt_division_with_unpacker' into main
2022-02-14 18:25:34 +00:00
ushakya22
df561f8550
work in progress exponent handling
2022-02-14 18:24:29 +00:00
David Harris
caa4d83e57
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
David Harris
9a71d77c4e
Improved makefile and synthesis script for parallel processing, max optimization
2022-02-14 01:22:17 +00:00
Ross Thompson
86e117ea77
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63
More cache cleanup.
2022-02-13 12:38:39 -06:00
ushakya22
a996a5e16c
Added unpacker into testbench for srt
2022-02-12 22:05:18 +00:00
David Harris
9e79f044c6
Enbled multicore synthesis
2022-02-12 06:44:58 +00:00
David Harris
f5678e25db
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
b537df2651
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
b1cba4be2b
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
20456097cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
David Harris
901a64e052
merged synth.tcl
2022-02-11 00:21:24 +00:00
David Harris
fdcb45d779
Waive some synthesis warning messages
2022-02-11 00:20:23 +00:00
