Jordan Carlin
|
21e35c9068
|
Lots more python cleanup
|
2024-12-17 16:32:49 -08:00 |
|
David Harris
|
147f62d9a5
|
Fixed timer offset in RV32 WALLY-wfi; simplified in RV64 WALLY-wfi
|
2024-11-17 06:43:13 -08:00 |
|
David Harris
|
205db4348c
|
Fixed cause_m_time_interrupt most significant byte
|
2024-11-16 18:31:02 -08:00 |
|
naichewa
|
73c2165756
|
recommit sckmode 10 11 delay regression tests
|
2024-11-05 11:30:13 -08:00 |
|
naichewa
|
9822902a4f
|
Revert "Added SCKMODE 10 and 11 delay cases to regression tests"
unwanted submodule changes
This reverts commit 38a88862ac.
|
2024-11-05 11:17:01 -08:00 |
|
naichewa
|
38a88862ac
|
Added SCKMODE 10 and 11 delay cases to regression tests
|
2024-11-04 16:22:42 -08:00 |
|
naichewa
|
3fda7ecb81
|
Fix SPI regression tests
|
2024-11-01 13:09:41 -07:00 |
|
naichewa
|
960d72295c
|
Removed SPI hardware interlock test cases
|
2024-11-01 11:27:41 -07:00 |
|
Rose Thompson
|
8fb1673ab3
|
Updated email address authorship for my files.
|
2024-10-15 10:27:53 -05:00 |
|
naichewa
|
3b7661dfd5
|
SckDiv Zero bug fixes
|
2024-09-03 14:58:46 -07:00 |
|
Jacob Pease
|
d8b75440b6
|
With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
|
2024-08-20 16:24:37 -05:00 |
|
David Harris
|
b3661a0af4
|
Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead
|
2024-03-24 12:31:49 -07:00 |
|
David Harris
|
9ff9f9e0ae
|
Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.
|
2024-03-14 19:03:57 -07:00 |
|
David Harris
|
824bc0dab7
|
Fixed expected value on WALLY-satp-invalid
|
2024-02-16 11:12:57 -08:00 |
|
David Harris
|
b362320dd9
|
Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof
|
2024-02-16 06:46:49 -08:00 |
|
David Harris
|
d094201362
|
Added NO_SAIL to wally-riscv-arch-test cases that stopped passing in Sail
|
2024-02-16 06:27:49 -08:00 |
|
David Harris
|
d9003da8e0
|
Moved some tests to wally-riscv-arch-test list that are simulated
|
2024-01-30 10:28:51 -08:00 |
|
naichewa
|
8b60992e72
|
fixed SPI tests failing when no icache
|
2024-01-17 14:38:11 -08:00 |
|
Rose Thompson
|
0b2af0c99a
|
Modifed the sv39 tests so they work with just 128MiB physical memory.
|
2024-01-12 20:00:21 -06:00 |
|
Rose Thompson
|
e6a2595936
|
Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.
|
2024-01-12 11:05:06 -06:00 |
|
Rose Thompson
|
70d0169019
|
All regression tests which matter are running!
|
2023-12-20 14:57:52 -06:00 |
|
Rose Thompson
|
1b59182d59
|
Updated tests with ending label.
|
2023-12-20 14:55:37 -06:00 |
|
Rose Thompson
|
49b1b7c7f9
|
Fixed the last uninitialized memory issue in the priv tests.
|
2023-12-19 16:51:56 -06:00 |
|
Rose Thompson
|
b04ad23c33
|
Fixed bugs in the wally64periph signature.
|
2023-12-19 16:16:59 -06:00 |
|
Rose Thompson
|
726efee1e2
|
Fixed bugs in the cbom test.
|
2023-12-19 15:53:48 -06:00 |
|
Rose Thompson
|
418ae0decc
|
Fixed some regression tests with David's help.
|
2023-12-19 14:18:21 -06:00 |
|
David Harris
|
29f57958a9
|
Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
|
2023-12-14 15:32:36 -08:00 |
|
David Harris
|
166c98b6f6
|
Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
|
2023-12-13 19:43:17 -08:00 |
|
David Harris
|
6c017141c5
|
Renamed HADE to ADUE for Svadu
|
2023-12-13 11:49:04 -08:00 |
|
Rose Thompson
|
9dfe421c55
|
Yay! Zicclsm passes my regression test now.
|
2023-11-10 18:28:51 -06:00 |
|
Rose Thompson
|
c0e02ae190
|
Found another bug in the RTL's Zicclsm alignment.
|
2023-11-10 18:26:55 -06:00 |
|
Rose Thompson
|
02ab9fe99c
|
Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
|
2023-11-10 17:58:42 -06:00 |
|
Rose Thompson
|
bd866e1025
|
Fixed some more bugs in the Zicclsm signature.
|
2023-11-10 17:36:10 -06:00 |
|
Rose Thompson
|
efecb0c346
|
Fixed bug in the Zicclsm test.
|
2023-11-10 17:34:23 -06:00 |
|
Rose Thompson
|
ada354f443
|
Fixed bug in the misaligned access test.
|
2023-11-10 17:02:15 -06:00 |
|
Rose Thompson
|
b74bfbeefd
|
Merge branch 'main' into Zicclsm
|
2023-11-10 16:15:32 -06:00 |
|
naichewa
|
d67badfc60
|
fix hardware interlock, hold mode deassert
|
2023-11-08 15:20:51 -08:00 |
|
naichewa
|
a5837eb62c
|
fifo fixes and edge case testing
|
2023-11-07 17:59:46 -08:00 |
|
naichewa
|
4651b807ed
|
added test cases
|
2023-11-02 15:43:08 -07:00 |
|
Rose Thompson
|
0a4ed5515b
|
Merge branch 'main' into Zicclsm
|
2023-11-02 12:55:51 -05:00 |
|
Rose Thompson
|
afa1d85e3b
|
Doesn't yet fully work.
Thomas is going to finish debugging while I'm on the RISCV summit next week.
|
2023-11-02 12:07:42 -05:00 |
|
Rose Thompson
|
7ba891f607
|
Progress. I think the remaining bugs are in the regression test's signature.
|
2023-11-01 17:51:48 -05:00 |
|
naichewa
|
9aa8a7af3e
|
comments, more test cases
|
2023-11-01 01:26:34 -07:00 |
|
Rose Thompson
|
5660eff57d
|
Working through issues with the psill logic.
|
2023-10-31 18:50:13 -05:00 |
|
Rose Thompson
|
4984b3935f
|
Progress
|
2023-10-31 14:50:33 -05:00 |
|
Rose Thompson
|
5ca428d6a8
|
Fixed bugs in misaligned test.
|
2023-10-31 12:49:35 -05:00 |
|
Rose Thompson
|
c061440141
|
First stab at the misaligned test.
|
2023-10-31 12:30:10 -05:00 |
|
naichewa
|
7dd3f24d6c
|
Merge branch 'main' into spi
|
2023-10-30 17:01:41 -07:00 |
|
naichewa
|
2330f4ee63
|
hardware interlock
|
2023-10-30 17:00:20 -07:00 |
|
Rose Thompson
|
2241976d29
|
Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
|
2023-10-30 18:26:11 -05:00 |
|