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Author	SHA1	Message	Date
David Harris	1bd639be6d	code cleanup	2022-12-01 08:15:48 -08:00
David Harris	4ddc8fd603	signal sufixes in integer division	2022-11-30 15:15:37 -08:00
cturek	10c2d45888	div tests in sim-wally	2022-11-30 02:32:04 +00:00
Ross Thompson	453ea36512	Optimization of cacheway.	2022-11-29 18:30:47 -06:00
Ross Thompson	fbf543bf57	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
Ross Thompson	0277227323	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-29 14:57:38 -06:00
Ross Thompson	b5718c9baa	Fixed a bug with the replacement policy. It was updating the wrong set on load hits.	2022-11-29 14:51:09 -06:00
Ross Thompson	96cc4c7ebe	Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.	2022-11-29 14:09:48 -06:00
Kip Macsai-Goren	c7c578c104	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-29 10:43:44 -08:00
Kip Macsai-Goren	44ea8d8b22	added failing satp invalid tests to regression	2022-11-29 10:43:38 -08:00
Ross Thompson	da82ab3712	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-29 11:52:35 -06:00
Ross Thompson	78acd40424	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
Kip Macsai-Goren	9b1765ce92	added tests for invalid address being written to satp. Not passing regression	2022-11-27 13:22:35 -08:00
Ross Thompson	6dd5668d21	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-22 18:07:32 -06:00
cturek	bdb9e24a66	Almost done with Int division	2022-11-22 22:22:59 +00:00
cturek	78c2ce5649	Updated testbench/wave for fdivsqrt new start signals	2022-11-22 22:22:26 +00:00
Ross Thompson	279f5bc615	Cleanup cacheLRU.	2022-11-22 14:59:01 -06:00
Ross Thompson	e1dbe58632	File name change for cachereplacement policy to cacheLRU	2022-11-20 22:35:02 -06:00
Ross Thompson	4e926ba4cf	Signal name changes for LRU.	2022-11-20 22:31:36 -06:00
Ross Thompson	e99a424ddc	Updated top level fpga file.	2022-11-18 11:10:45 -06:00
Ross Thompson	d67ba9e55a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-17 17:45:59 -06:00
Ross Thompson	00218d559f	Missing a file. Last commit will fail.	2022-11-17 17:45:41 -06:00
Ross Thompson	47e1d1764b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-17 17:38:52 -06:00
Ross Thompson	0106777f02	Finally have the correct replacement policy implementation.	2022-11-17 17:36:37 -06:00
Ross Thompson	70d7fca750	Updated fpga wave configuration.	2022-11-16 15:57:19 -06:00
Ross Thompson	6ad9ba1e73	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-16 15:39:17 -06:00
Ross Thompson	faa13a96e0	I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.	2022-11-16 15:38:37 -06:00
Ross Thompson	22ad49eef2	Progress on the cache replacement policy implementation.	2022-11-16 15:35:34 -06:00
Ross Thompson	847af7b95c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-16 12:44:06 -06:00
Ross Thompson	0796cd92fc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-16 12:42:29 -06:00
Ross Thompson	42111db671	Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.	2022-11-16 12:36:58 -06:00
David Harris	59335ac70f	comment cleanup	2022-11-16 10:23:20 -08:00
David Harris	be9c618c94	Renamed DivBusy to FDivBusyE in FPU	2022-11-16 10:13:27 -08:00
David Harris	128cc86254	Moved DivStartE to fdivsqrtfsm	2022-11-16 10:00:07 -08:00
Ross Thompson	1f21a2bab1	Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.	2022-11-16 11:15:34 -06:00
Ross Thompson	e24378db8f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-15 14:49:32 -06:00
cturek	ffd03e9548	Attempt to fix FPGA synth errors	2022-11-15 20:34:28 +00:00
cturek	98b66aab9f	Fixed lint errors in postprocessing	2022-11-15 20:31:23 +00:00
Ross Thompson	cf00f85456	Updated vcu118 constraints to run cpu at 38.43Mhz.	2022-11-15 10:19:38 -06:00
Ross Thompson	62d28d8cca	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-15 10:18:56 -06:00
Ross Thompson	3df51716b1	Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.	2022-11-14 16:02:20 -06:00
Ross Thompson	b53f8eceef	Renamed Flush to FlushStage in the cache.	2022-11-14 14:11:05 -06:00
Ross Thompson	284b97aff6	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-14 13:48:56 -06:00
David Harris	6372139af4	Removed comment about nonexistent possible bug	2022-11-14 09:56:33 -08:00
David Harris	06dbed92c8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-14 09:52:24 -08:00
David Harris	f9202187ba	Removed comment about nonexistent possible bug	2022-11-14 09:52:21 -08:00
Ross Thompson	13e6f7d80b	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
Ross Thompson	788ae5fb18	Updated wave file.	2022-11-13 21:34:45 -06:00
cturek	abaa33b92a	Added majority of combinational logic	2022-11-14 00:06:38 +00:00
cturek	6740d77b63	Added Quotient/Remainder calcs to normal termination	2022-11-13 23:44:34 +00:00