Ross Thompson
dd26b754eb
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
Ross Thompson
daf344f1ba
Updated branch predictor tests/benchmarks.
2021-05-24 11:13:33 -05:00
James E. Stine
194c32defa
Update header for FPadd
2021-05-24 08:28:16 -05:00
Katherine Parry
55f22979ca
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
bbracker
142b02b30a
improved PLIC test organization
2021-05-21 15:13:02 -04:00
James E. Stine
49a4097d97
Minor testbench updates to rv64icfd
2021-05-21 09:41:21 -05:00
James E. Stine
47487a625f
Update to testbench-imperase for rv64icfd
2021-05-21 09:28:44 -05:00
James E. Stine
694e21541b
Update to FLD/FSD testbench
2021-05-21 09:26:55 -05:00
James E. Stine
474d479280
Update to rv64icfd wally-config to run through FP tests
2021-05-21 09:22:17 -05:00
Katherine Parry
67a41748ba
FMV.D.X imperas test passes
2021-05-20 22:18:33 -04:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
114bba8370
small bit of busybear debug progress
2021-05-19 20:18:00 -04:00
bbracker
8554f2f3cd
plic implementation optimizations
2021-05-19 18:10:48 +00:00
bbracker
fd4fae0406
commented out MSTATUS test
2021-05-19 12:38:01 -04:00
James E. Stine
058b265d18
Update rv64icfd batch script
2021-05-18 16:01:53 -05:00
James E. Stine
f407bee5ae
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
2021-05-18 13:48:44 -05:00
bbracker
18ab9015f9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-18 14:33:40 -04:00
bbracker
f43ea946aa
changed lint script to use absolute path for verilator because cron jobs stink at using paths
2021-05-18 14:33:22 -04:00
David Harris
7dcc53dcf5
fixed rv64mmu makefile
2021-05-18 14:25:55 -04:00
David Harris
5f214d60b6
Removed rv64wally
2021-05-18 14:08:46 -04:00
David Harris
433ea61d9e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
2021-05-18 14:01:19 -04:00
Katherine Parry
409438bc95
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
bbracker
86d55cd07a
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
2021-05-17 19:25:54 -04:00
bbracker
69ef758e78
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
2021-05-17 18:44:47 -04:00
David Harris
1aa1908994
Deleted vish_stacktrace
2021-05-17 18:39:01 -04:00
James E. Stine
49cc330bd9
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
Elizabeth Hedenberg
853c9243c1
commit ehedenberg coremark
2021-05-17 18:02:35 -04:00
James E. Stine
96eca3287f
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
8822bdd6ad
Cleanup of regression
2021-05-17 16:58:15 -05:00
James E. Stine
41da78e0b6
Mod Imperas Testbench for updated Div/Rem
2021-05-17 16:56:30 -05:00
James E. Stine
97cbdae674
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e
Fix comment
2021-05-14 08:06:07 -04:00
Thomas Fleming
a191978a97
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-14 07:40:08 -04:00
Thomas Fleming
1fc607b399
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Thomas Fleming
980c00fa64
Clean up MMU code
2021-05-14 07:12:32 -04:00
Elizabeth Hedenberg
0fe798d5e1
pushing coremark to main branch
2021-05-11 21:33:39 -04:00
Jarred Allen
dc41623754
Minor fixes in regression
2021-05-09 13:57:09 -04:00
Jarred Allen
788680fa4d
Fix bug in regression script
2021-05-06 12:56:57 -04:00
Domenico Ottolia
f78f865e88
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 20:22:31 -04:00
Domenico Ottolia
1c884338b0
Forgot to add csr permission tests to testbench
2021-05-04 20:20:22 -04:00
Jarred Allen
15da77fe15
Clean up regression script and document it
2021-05-04 18:58:59 -04:00
ushakya22
6274c8cb80
Added mip tests to testbench
2021-05-04 15:36:06 -04:00
Thomas Fleming
1e0a5ef807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 15:22:21 -04:00
bbracker
535046e494
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Domenico Ottolia
14becde792
Re-add medeleg tests to testbench
2021-05-04 14:42:20 -04:00
Ross Thompson
619dcb165d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 13:04:20 -05:00
Ross Thompson
2aa4db470b
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
ushakya22
6a71aafadc
Updated CSR tests
2021-05-04 13:48:47 -04:00
Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Thomas Fleming
192878b124
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 03:14:38 -04:00
Thomas Fleming
dac07e34cf
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
ushakya22
da352c81e7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 02:22:17 -04:00
ushakya22
66344f0604
Added MIE tests to testbench
2021-05-04 02:22:01 -04:00
Thomas Fleming
d7fa0903bc
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Domenico Ottolia
2c39c0a6a5
Minor tweaks to mcause & scause tests
2021-05-04 01:33:49 -04:00
David Harris
7c2481bea6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 01:19:57 -04:00
David Harris
4db3780ebb
Fixed testbench to produce error when signature.output doesn't exist
2021-05-04 01:19:44 -04:00
Thomas Fleming
39135f221e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 01:14:13 -04:00
Domenico Ottolia
1556cc5b9f
Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE
2021-05-04 01:04:12 -04:00
Domenico Ottolia
84911e6345
Fix 32 bit privileged tests!!!
2021-05-04 00:16:19 -04:00
Thomas Fleming
4f5ef65aeb
Restore original order of tests
2021-05-03 23:50:21 -04:00
Thomas Fleming
d53afc8510
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Thomas Fleming
1f6db293fa
Enable mmu tests in testbench
2021-05-03 23:15:23 -04:00
Domenico Ottolia
a7e89f43c1
Fix bug with IllegalInstrFaultM not getting correct value
2021-05-03 22:48:03 -04:00
Domenico Ottolia
12d8ff617b
Run all tests
2021-05-03 22:38:59 -04:00
Domenico Ottolia
353d4e9238
Update cause tests to be longer
2021-05-03 22:38:26 -04:00
Domenico Ottolia
db4e447a25
Add mtvec and stvec tests to testbench
2021-05-03 22:19:50 -04:00
Shriya Nadgauda
c10d332c6e
working testbench-imperas
2021-05-03 22:16:58 -04:00
Shriya Nadgauda
0be6b81df9
finishing merge conflict changes
2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7
merge conflict fixes
2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7
updated pipeline tests
2021-05-03 22:07:36 -04:00
Thomas Fleming
f78f2b3b5d
Adjust attributes in PMA checker
2021-05-03 21:58:32 -04:00
David Harris
96e90402c5
Rolled back fflush on uart. Use -syncio in Modelsim command line instead.
2021-05-03 20:04:44 -04:00
David Harris
062120f944
Flush uart print statements on \n
2021-05-03 19:51:51 -04:00
David Harris
743011194b
Flush uart print statements on \n
2021-05-03 19:41:37 -04:00
David Harris
4285d60041
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:37:56 -04:00
David Harris
8758b6efa1
Flush uart print statements on \n
2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
08bfaeffe3
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c
coremark updates
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06
coremark directory changes
2021-05-03 19:35:06 -04:00
David Harris
2f5649832a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Domenico Ottolia
e59f8037be
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:56:05 -04:00
Ross Thompson
21c0ee0cf2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Jarred Allen
a21b84e2ad
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
David Harris
699a8f3ac3
Extended maximum signature length to 1M
2021-05-03 15:29:20 -04:00
Katherine Parry
3f05e31954
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00