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9,549 Commits 4 Branches 2 Tags 53 MiB
167878aee4
Commit Graph

340 Commits

Author SHA1 Message Date
Rose Thompson
167878aee4 Commet out debug code in fpga synth script. 2024-08-23 14:46:01 -07:00
Rose Thompson
b471913d9f On the way to making vcu108 work again. 2024-08-23 14:45:22 -07:00
Rose Thompson
4d56b3ca96 Maybe improvements to fpga synthesis. 2024-08-23 13:00:22 -07:00
Rose Thompson
fc80bf1251 More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
Rose Thompson
8d40a0a092 Changed names of fpga IP modules to match textbook. Updated boot.h to 
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
 2024-08-22 13:56:50 -07:00
Rose Thompson
faffecf891 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:17 -07:00
Rose Thompson
01b623b8c4 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:08 -07:00
Rose Thompson
113d71f1a0 More name updates. 2024-08-21 10:51:24 -07:00
Rose Thompson
f603d21826 Updated my name in multiple locations. 2024-08-21 10:50:39 -07:00
Jacob Pease
baad4e0fd2 With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests. 2024-08-20 16:24:37 -05:00
Jacob Pease
9ac889e3e8 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
Jacob Pease
4a1abb1d17 Added dynamic SDC Clock selector in bootloader code. 2024-08-20 12:19:49 -05:00
Jordan Carlin
4d68664e32 FPGA Makefile refactoring 2024-08-15 11:58:40 -07:00
Rose Thompson
375b0d0638 Merge pull request #902 from jordancarlin/build_zsbl 
Build zsbl in main Makefile
 2024-08-15 07:49:07 -07:00
Jordan Carlin
6d77398c95 Update linker scripts to avoid hardcoded /opt/riscv 2024-08-09 20:15:28 -07:00
Jordan Carlin
08506b5872 Remove boot.mem 2024-08-08 20:27:51 -07:00
David Harris
77c2a86cef Merge pull request #869 from jordancarlin/installation 
Installation and setup overhaul
 2024-08-08 15:39:23 -07:00
Jacob Pease
6e8c210e09 Commented out rvvi debug probes in wally.tcl. 2024-08-08 13:52:53 -05:00
Jacob Pease
660da55451 Turned off RVVI by default. 2024-08-08 13:50:11 -05:00
Jordan Carlin
357175f1c8 Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-08-07 20:22:55 -07:00
Jacob Pease
f8f16d2d34 Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
Jacob Pease
89ecc10451 Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
Jacob Pease
9f5c3fb66a Removed line referring to local file in wally.tcl. 2024-08-06 17:11:08 -05:00
Jacob Pease
11ca2567b8 Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-08-06 17:09:39 -05:00
Jacob Pease
8b85a5c34a SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree. 2024-08-06 16:57:57 -05:00
Jacob Pease
173562d6f4 Added file necessary to split boot.mem into boot.mem and data.mem. 2024-08-02 15:36:06 -05:00
Jacob Pease
51f061ba35 Removed HSELEXTSDC and fixed SD card pin definitions. 2024-08-02 15:35:18 -05:00
Jacob Pease
bd07a60c07 Updated wally source files for zsbl testing. 2024-08-02 15:33:57 -05:00
Jacob Pease
1edd5bb39e New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently. 2024-08-02 15:19:52 -05:00
Jacob Pease
3fde6c13f7 Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display. 2024-08-02 15:14:30 -05:00
Jacob Pease
906fa73747 Updated formatting of gpt.c and boot.c. 2024-07-31 11:12:05 -05:00
Jacob Pease
0396181d1e Added function to set SPI clock speed. 2024-07-31 11:00:44 -05:00
Jacob Pease
826576bfc7 Cleaned up code formatting a bit and added ability to set the SD card clock speed. 2024-07-31 10:59:41 -05:00
Jacob Pease
5d6699dc4c Added extra UART macros and functions for code readability and the ability to print decimal numbers. 2024-07-31 10:58:15 -05:00
Jordan Carlin
e78fac1624 Replace /opt/riscv after merge 2024-07-25 21:33:31 -07:00
Jordan Carlin
2f1a101735 Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-25 21:21:57 -07:00
Jacob Pease
8a5898ebc1 Added carriage returns to line feed characters. UART messages print properly now. 2024-07-25 13:05:57 -05:00
Jacob Pease
f12319ca96 Changed formatting and added new UART divsor calculation from OpenSBI. 2024-07-25 13:04:27 -05:00
Jacob Pease
6fc10adc25 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
02bb9b0b8b Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
a34836c08b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
ffec8cfb20 Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
36d330a173 Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
a97c7f0b58 Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
e175a41863 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Rose Thompson
994386f12c Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
13db14db6b Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Jacob Pease
c18b3d814d Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
23d9c7a486 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00