Ross Thompson
0e2352a6de
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21
Added possibly working OSU test bench as a precursor to running a bp benchmark.
...
Fixed a few bugs with the function radix.
2021-03-17 11:06:32 -05:00
Noah Boorstin
45ed2742cf
busybear: add seperate message on bad memory access becasue its confusing
2021-03-16 21:42:26 -04:00
Domenico Ottolia
c9d70a1778
Add privileged testbench
2021-03-16 20:28:38 -04:00
Noah Boorstin
6d8bcfe6bf
copy Ross's branch predictor preload change into busybear
2021-03-15 18:27:27 -04:00
Ross Thompson
8e51935082
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Ross Thompson
0edaa625e3
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-12 20:16:03 -06:00
Ross Thompson
ccaaa829ce
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
David Harris
4465854423
Drafted rv32a tests
2021-03-12 00:06:23 -05:00
David Harris
d4e84c58ed
64-bit AMO debugged
2021-03-11 23:18:33 -05:00
Ross Thompson
b1d1f3995c
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 17:12:21 -06:00
Noah Boorstin
f31d7a7f5c
busybear: account for CSR moving
2021-03-11 06:45:14 +00:00
Ross Thompson
f1f7884e10
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Ross Thompson
7b7cacbaf0
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
David Harris
0baa004bb4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
87e2a9b920
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
1fc00d41c2
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Noah Boorstin
f0a103687e
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
464c1de03d
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Ross Thompson
7902c3fdb6
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Noah Boorstin
cfcd7d1518
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Noah Boorstin
fde94f9057
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
bbracker
7852d866ef
JALR testing
2021-03-04 10:37:30 -05:00
Teo Ene
d3a1afe50e
Fix to last push
2021-03-03 15:20:38 -06:00
Noah Boorstin
923489fe16
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
b6dc0a8707
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Noah Boorstin
a267115635
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
932bc0ef85
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
0596d61a2a
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
kaveh pezeshki
e8b306bcba
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6
restored
2021-02-26 02:22:08 -08:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
kaveh pezeshki
251aa982eb
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
kaveh pezeshki
06f73fe5fe
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
