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Author SHA1 Message Date
David Harris
09aebbf252 Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
Rose Thompson
455b78362c Merge pull request #449 from davidharrishmc/dev 
Synthesis cleanup
 2023-11-02 12:26:55 -05:00
David Harris
bf65ce0f9f Removed .gitattributes 2023-11-01 17:50:44 -07:00
David Harris
31d9ec08cb Improved comments about memory read paths 2023-11-01 07:00:17 -07:00
David Harris
dccd7bf5ee Fixes to config extraction 2023-10-31 06:27:55 -07:00
David Harris
5112bfed19 130 nm synthesis script improvements 2023-10-30 20:57:35 -07:00
David Harris
680fb3f30b Conditionally instantiate hardware in ifu 2023-10-30 20:55:00 -07:00
David Harris
afabc52b61 Gated InstrOrigM and PCMReg when not needed 2023-10-30 20:05:37 -07:00
David Harris
2d17a991d8 rom1p1r code cleanup 2023-10-30 19:47:49 -07:00
David Harris
3f7c67882f rom1p1r code cleanup 2023-10-30 19:46:38 -07:00
David Harris
90a178e31e Made 2-bit AdrReg conditional on being needed 2023-10-30 19:13:43 -07:00
Rose Thompson
89de8cd23c Merge pull request #445 from davidharrishmc/dev 
Fix issue 444; no delegating misaligned instructions if they can't happen
 2023-10-30 12:25:42 -05:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
27b8ebb9bd Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported. 2023-10-30 07:06:34 -07:00
Rose Thompson
50a1d731c0 Merge pull request #443 from davidharrishmc/dev 
Wrapper synthesis fix.
 2023-10-27 09:25:06 -05:00
David Harris
09c4aaa5d9 Fixed reporting of timing on modules with wrappers 2023-10-26 20:14:14 -07:00
David Harris
734bf021d7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
David Harris
8cf81a2bb8 Merge pull request #441 from ross144/main 
Fixed issues #200
 2023-10-26 10:26:58 -07:00
Rose Thompson
06b5a92eff Updated comments about Interrupt and wfi. 2023-10-26 12:24:36 -05:00
Rose Thompson
4cd0584a11 Forgot to include this file in the last commit. 2023-10-26 12:20:42 -05:00
Rose Thompson
14f8b4849f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-26 12:15:22 -05:00
Rose Thompson
3322ff915e Cleaned up the implementation changes for wfi. 2023-10-24 23:11:48 -05:00
Rose Thompson
c58f04c901 This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps. 2023-10-24 22:58:26 -05:00
Rose Thompson
c61526d034 Possible fix for wfi. 2023-10-24 18:08:33 -05:00
David Harris
3bb7539429 Fixed warnings of signed conversion and for Design Compiler 2023-10-24 14:01:43 -07:00
David Harris
905c5da7a9 Tested assembly language file for the pause example 2023-10-24 10:45:41 -07:00
David Harris
ea571a6e3b Merge pull request #439 from ross144/main 
Fixes to branch predictor processing scripts.
 2023-10-24 08:31:06 -07:00
Rose Thompson
bd04ffc0c9 Fixed bug in bpred-sim.py for btb and class size sweep. 2023-10-24 10:29:02 -05:00
Rose Thompson
4fe58fe036 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-23 16:14:30 -05:00
Rose Thompson
ea403e02ff Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction. 2023-10-23 16:09:40 -05:00
Rose Thompson
694ec18934 Added support for branch counters when there is no branch predictor. 2023-10-23 15:32:03 -05:00
Rose Thompson
1611d5ec3c Fixed issue 250. instruction classification was not correct for jalr ra (non zero). 2023-10-23 15:30:43 -05:00
Rose Thompson
2aecf688f9 Addeed script to sweep sim_bp for btb. 2023-10-23 15:29:50 -05:00
David Harris
eba346849c Merge pull request #438 from ross144/main 
Fixed comments in cboz and cbom tests.
 2023-10-20 17:15:59 -07:00
Rose Thompson
0fd5b3b2ce Updated comments in the cboz tests. 2023-10-20 15:15:47 -05:00
Rose Thompson
0aea2c80b8 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-20 15:14:02 -05:00
Rose Thompson
5a4028064a Updated comments for the cbom tests. 2023-10-20 15:13:52 -05:00
Rose Thompson
d6dcec458d Merge pull request #437 from davidharrishmc/dev 
synth improvements
 2023-10-19 16:23:34 -05:00
David Harris
cbf0c01fd6 Set drive for Sky130 2023-10-19 13:46:30 -07:00
David Harris
6e7c0547a1 Modified log2 coding to avoid synthesis warning 2023-10-19 11:16:02 -07:00
Rose Thompson
a12fb6a338 Merge pull request #436 from davidharrishmc/dev 
Automatic generation of synthesis wrappers when needed
 2023-10-19 12:51:24 -05:00
David Harris
8f717c3254 Removed wrapper from wallySynth because it is automatic now 2023-10-19 10:49:06 -07:00
David Harris
348e74b8be Updated wrapper generation to be automatic without specifying WRAPPER=1; instead looks for cvw_t in the file. Also starting to add OSU 130 nm synthesis. 2023-10-19 10:44:03 -07:00
David Harris
7c1606264a Adjusted synthesis scripts to report on DESIGN even when a wrapper is used 2023-10-19 06:16:52 -07:00
Rose Thompson
83c354c4a1 Merge pull request #434 from davidharrishmc/dev 
Config and peripheral cleanup
 2023-10-18 17:58:29 -05:00
David Harris
4873b9c0a8 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-18 14:40:19 -07:00
David Harris
4469484f4a Merge pull request #435 from kipmacsaigoren/synth_wrapper_gen 
synth wrapper generation bug fix
 2023-10-18 14:34:37 -07:00
Kevin Kim
7b35da5245 wrapper bug fix 2023-10-18 14:29:46 -07:00
David Harris
48d42c1e7c Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates 2023-10-18 05:50:41 -07:00
David Harris
b76c371e45 Config file cleanup 2023-10-18 05:38:36 -07:00