Github_Repos/cvw
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10,326 Commits 4 Branches 2 Tags 52 MiB
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47 Commits

Author SHA1 Message Date
Jacob Pease
9c39371657 Reverted bootloader optimizations to second iteration. Working on last optimization. 2024-11-02 14:14:31 -05:00
Rose Thompson
816e54f451 Revert "Revmoed file from fpga zbbl which should not have been added." 
This reverts commit d6944cdaa4.
 2024-10-14 21:29:02 -05:00
Rose Thompson
d6944cdaa4 Revmoed file from fpga zbbl which should not have been added. 2024-10-03 15:03:15 -05:00
Jordan Carlin
022b98a64b
Update all iterative makes to use 2024-09-29 23:14:19 -07:00
Rose Thompson
8248f2dd66 Added MAXSDCCLOCK to parameters set by the FPGA makefile. 2024-09-03 10:55:15 -07:00
Rose Thompson
4afdb500d7 Added missing files. 2024-09-02 14:46:41 -07:00
Rose Thompson
869860bc55 Merge branch 'main' of github.com:ross144/cvw 2024-09-02 14:08:48 -07:00
Rose Thompson
9471ccd2fc Updated Makefiles and source files to build the zsbl according to the config. 2024-09-02 14:03:47 -07:00
Rose Thompson
2e55f1cecc Well on the way to a fully automated FPGA build process which 
correctly sets the clocks and memory locations.
 2024-09-02 11:19:02 -07:00
Jacob Pease
44ece7cb96 Added CVW header to spitest files. 2024-08-27 14:28:49 -05:00
Jacob Pease
d649473ec8 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-24 21:57:44 -05:00
Jacob Pease
ad6734eb6d Improved the speed of the bootloader by 60s. CRC16 is now calculated with a table and a byte is now sent for every byte read, keeping the FIFO full. 2024-08-24 21:36:29 -05:00
Rose Thompson
8d40a0a092 Changed names of fpga IP modules to match textbook. Updated boot.h to 
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
 2024-08-22 13:56:50 -07:00
Jacob Pease
43b17b5058 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
Jacob Pease
9fae5dfc0a Added dynamic SDC Clock selector in bootloader code. 2024-08-20 12:19:49 -05:00
Jordan Carlin
564ce83e11
Update linker scripts to avoid hardcoded /opt/riscv 2024-08-09 20:15:28 -07:00
Jacob Pease
2dc7e0f76f Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
Jacob Pease
280b5baa59 Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
Jacob Pease
665396fdb3 SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree. 2024-08-06 16:57:57 -05:00
Jacob Pease
ad9c98c19c Added file necessary to split boot.mem into boot.mem and data.mem. 2024-08-02 15:36:06 -05:00
Jacob Pease
897f6561cd New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently. 2024-08-02 15:19:52 -05:00
Jacob Pease
fcd88d6e6f Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display. 2024-08-02 15:14:30 -05:00
Jacob Pease
38071d8267 Updated formatting of gpt.c and boot.c. 2024-07-31 11:12:05 -05:00
Jacob Pease
ee980e39f3 Added function to set SPI clock speed. 2024-07-31 11:00:44 -05:00
Jacob Pease
c4ae17c679 Cleaned up code formatting a bit and added ability to set the SD card clock speed. 2024-07-31 10:59:41 -05:00
Jacob Pease
a263f836f2 Added extra UART macros and functions for code readability and the ability to print decimal numbers. 2024-07-31 10:58:15 -05:00
Jacob Pease
3975f60299 Added carriage returns to line feed characters. UART messages print properly now. 2024-07-25 13:05:57 -05:00
Jacob Pease
a36e846b02 Changed formatting and added new UART divsor calculation from OpenSBI. 2024-07-25 13:04:27 -05:00
Jacob Pease
336a413f31 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
d15be492cb Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
286d80de7e Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
0107a400d1 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jacob Pease
dcb2edf888 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Jacob Pease
5f0addd69a Initial pass on SPI based bootloader code finished. 2024-07-23 16:33:49 -05:00
Jacob Pease
a8b9e7776b Added some minor error checking to gpt.c. 2024-07-23 16:32:52 -05:00
Jacob Pease
ab00ea5a5c Added sd_read64 to help with block reads and crc checking. 2024-07-23 16:32:29 -05:00
Jacob Pease
57eeba5c8c Progress made on implementing new disk read function. 2024-07-23 15:47:23 -05:00
Jacob Pease
9ccb0eb027 Removed references to card_type. 2024-07-23 15:46:18 -05:00
Jacob Pease
bf65cd2817 Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c 2024-07-23 14:18:42 -05:00
Jacob Pease
b05052311f Added sd_cmd and utility SPI functions. 2024-07-22 16:57:04 -05:00
Jacob Pease
e91d2c8b14 Corrected the CRC7 code with the right sequence of instructions. 2024-07-22 01:19:10 -05:00
Jacob Pease
c7d869bc96 Added inital spi based sd card code. Working on CRC7 code that works. 2024-07-20 14:00:43 -05:00
Jacob Pease
53b2a51c89 Added tentative spi_send_byte function. 2024-07-19 12:30:32 -05:00
Jacob Pease
34e89e842c Added initial spi code to fpga/zsbl 2024-07-19 11:35:12 -05:00
Jacob Pease
7a417d7a6c Added true bootloader to fpga/zsbl directory. 2024-05-31 15:28:25 -05:00
Rose Thompson
6097444b5a Added missing file for compiling the fpga zero stage bootloader. 2024-04-11 10:30:56 -05:00
Rose Thompson
60f96112db Moved the zero stage boot loader to the fpga directory. 2024-03-01 10:23:55 -06:00