David Harris
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3f195884e9
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Defined bit sizes more precisely to help VCS lint and conform to coding style
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2024-04-21 08:40:11 -07:00 |
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David Harris
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1759c920bb
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improved regression comments
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2024-04-21 08:38:59 -07:00 |
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David Harris
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be15a11622
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Fixed conflicts on getenv
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2024-04-21 08:38:13 -07:00 |
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David Harris
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0419b5484a
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parameterized register names in peripherals
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2024-04-21 07:43:01 -07:00 |
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David Harris
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00a1c0fc57
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Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
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2024-04-21 00:02:15 -07:00 |
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David Harris
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1817ab2e11
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testbench import is happy now for Questa, but throws lint warning for VCS
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2024-04-20 23:13:13 -07:00 |
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David Harris
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fd6a6b2249
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environment variable cleanup
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2024-04-20 22:52:08 -07:00 |
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David Harris
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f39e240082
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Spacing cleanup
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2024-04-20 20:53:49 -07:00 |
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David Harris
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25a26656b6
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Removed unnecessary ZBB from BMU extract mux
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2024-04-20 20:53:14 -07:00 |
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David Harris
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a1876b1e7c
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script cleanup
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2024-04-20 17:22:31 -07:00 |
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David Harris
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338f37b570
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Moved getenv/getenvval declaration to config-shared so lint and regression both run
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2024-04-20 17:19:42 -07:00 |
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David Harris
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571b67f565
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Merging PR738
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2024-04-20 17:15:17 -07:00 |
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David Harris
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e467e46967
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Merge pull request #738 from slmnemo/linux_nightly
Added full Linux boot to regression-wally
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2024-04-20 17:08:43 -07:00 |
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slmnemo
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f0229e970b
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Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench.
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2024-04-20 17:07:54 -07:00 |
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slmnemo
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66a002d879
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Removed unused rmCmd string declaration
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2024-04-20 16:58:23 -07:00 |
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slmnemo
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354d447269
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Changed testbench to use fopen instead of opening and closing uartfile whenever writing
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2024-04-20 16:56:54 -07:00 |
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slmnemo
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770d918268
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Split buildroot and buildrootboot into separate tests to prevent squashing. Removed extraneous comments.
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2024-04-20 16:39:05 -07:00 |
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slmnemo
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04ac4007ec
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Updated tuple to name logfile to grepfile to better reflect purpose in regression. Added -a to grep so it works iwth binary files
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2024-04-20 16:08:08 -07:00 |
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David Harris
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ea344fe2fa
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Fixed getenvval lint error in rom1p1r
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2024-04-20 15:55:52 -07:00 |
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David Harris
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a3db61b2b2
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-04-20 15:41:42 -07:00 |
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slmnemo
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6458fa5642
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Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly
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2024-04-20 14:46:35 -07:00 |
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David Harris
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f639cf4d47
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wsim invokes vcs
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2024-04-20 14:23:21 -07:00 |
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David Harris
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3cb5cd0cb1
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simulator cleanup
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2024-04-20 14:12:55 -07:00 |
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David Harris
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800bdc290f
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Increased ulimit for Verilator
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2024-04-20 13:40:30 -07:00 |
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David Harris
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f790d67aa7
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Merge pull request #745 from Karl-Han/rom_wally_env
Add getenvval for rom. Related to issue #723.
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2024-04-20 13:29:28 -07:00 |
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David Harris
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b7e66ec7d6
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Added Zcb tests to riscof
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2024-04-20 13:17:33 -07:00 |
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David Harris
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d9ebfdfc4f
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Enabled Zcb tests
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2024-04-20 13:16:54 -07:00 |
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David Harris
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9ec4c752f1
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Fixed bugs in Zcb compressed loads and stores
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2024-04-20 13:16:31 -07:00 |
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David Harris
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0fc66268f8
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coremark sweep cleanup
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2024-04-20 12:44:44 -07:00 |
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David Harris
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c8e7a6990d
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-04-20 11:44:27 -07:00 |
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David Harris
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bf2f6859e4
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Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere
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2024-04-20 11:27:54 -07:00 |
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David Harris
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84e8d86d2a
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Merge pull request #739 from Karl-Han/deriv_support
Add extra path to search for deriv/buildroot
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2024-04-20 11:23:54 -07:00 |
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slmnemo
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9e3622b4ec
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Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly
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2024-04-20 11:23:33 -07:00 |
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Rose Thompson
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408af3cac3
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Merge pull request #744 from quswarabid/update_addins
updated the submodules -> riscv-arch-tests and riscv-dv
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2024-04-18 12:31:11 -05:00 |
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Kunlin Han
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08dd2eac74
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Add getenvval for rom. Related to issue #723.
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2024-04-17 23:26:09 -07:00 |
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Rose Thompson
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f94aab2d0d
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Merge pull request #743 from quswarabid/tb_fix_uncore
the fix in testbench-imperas for uncore part of soc (unresolved reference)
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2024-04-17 12:56:27 -05:00 |
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slmnemo
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2b0cf90a99
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Merged with merge conflict
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2024-04-17 10:47:28 -07:00 |
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slmnemo
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d39f1ebefc
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Less hacky implementation of simulation log and searched log
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2024-04-17 10:41:12 -07:00 |
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slmnemo
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b5ef66dc3c
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Less hacky implementation of the same method as before
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2024-04-17 10:26:30 -07:00 |
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Quswar Abid
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6f16b7e0c9
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updated the submodules -> riscv-arch-tests and riscv-dv
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2024-04-17 10:25:36 -07:00 |
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Kunlin Han
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91a88fa46c
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Update sim/verilator/Makefile with more comments and merging variables.
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2024-04-17 09:52:54 -07:00 |
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Quswar Abid
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1b18568d87
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the fix Rose provided in meeting
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2024-04-17 09:39:21 -07:00 |
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David Harris
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9a29668d1e
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Merge pull request #737 from ross144/main
Fixed code coverage for regression-wally
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2024-04-17 08:37:15 -06:00 |
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Rose Thompson
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416b138cf5
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Merge pull request #740 from davidharrishmc/dev
Simplify shiftcorrection module
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2024-04-17 09:19:30 -05:00 |
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David Harris
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7abf98cb4d
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Reordered coremark sweep to match text
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2024-04-17 04:03:48 -07:00 |
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David Harris
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c11daf43f0
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removed extranious iteration flag from makefile
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2024-04-17 04:02:58 -07:00 |
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David Harris
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45c32bbcdf
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Fixed zbc to zbs to use full bit manipulation instructions in CoreMark
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2024-04-17 04:02:06 -07:00 |
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David Harris
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5fdf8dfbec
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Switched back to unsigned ints for RV32 CoreMark per spec. CM/MHz rises from 3.35 to 3.36
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2024-04-17 04:01:25 -07:00 |
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David Harris
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3ea16c6057
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Removed note about store stall being depricated
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2024-04-17 03:34:11 -07:00 |
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David Harris
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cd9c2e0e2b
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Updated embench Makefile to refer to generic sim, rather than modelsim
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2024-04-17 03:16:01 -07:00 |
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