David Harris 16f3c25cb7 sram1p1rw cleanup		2022-12-20 02:57:51 -08:00
..
cache	I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.	2022-12-18 18:30:35 -06:00
ebu	Rough draft of cache flush fsm enhancement.	2022-12-16 15:28:22 -06:00
fpu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-12-19 09:09:57 -08:00
generic	sram1p1rw cleanup	2022-12-20 02:57:51 -08:00
hazard	Explained hazard causes	2022-12-19 09:41:41 -08:00
ieu	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
ifu	Renamed SRAM2P1R1W to lower case	2022-12-20 02:09:36 -08:00
lsu	Cleanup comments.	2022-12-16 17:08:35 -06:00
mmu	Moved CPUBusy out of HPTW.	2022-12-11 15:48:00 -06:00
muldiv	Use FlushE to reset integer divider FSM	2022-12-15 11:00:54 -08:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Replaced || and && with single ops	2022-12-20 01:33:35 -08:00
uncore	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
wally	Renamed FStallD to FPUStallD.	2022-12-19 09:28:45 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00