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  • 42aee1db30 hptw: renamed DTLBMissQ to DTLBWalk David Harris 2021-07-17 14:13:00 -0400
  • 58874b19fc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Abe 2021-07-17 14:05:19 -0400
  • 6f22e9a393 hptw: renamed ADRE to ADR David Harris 2021-07-17 14:02:59 -0400
  • 3ce22a60b3 hptw: replaced PreviousWalkerState with a PageType FSM David Harris 2021-07-17 13:54:58 -0400
  • 89fd653cc1 hptw: removed ITLBMissFQ David Harris 2021-07-17 13:44:08 -0400
  • 87aa527de7 hptw: minor cleanup David Harris 2021-07-17 13:40:12 -0400
  • ea2aa469a1 hptw: Simplifed out AnyTLBMiss David Harris 2021-07-17 12:07:51 -0400
  • 784e6cf538 hptw: Renamed Memstore to MemWrite David Harris 2021-07-17 12:01:43 -0400
  • 0a6622a6fb hptw: Merged RV32/64 FSMs David Harris 2021-07-17 11:55:24 -0400
  • cf0975c937 hptw: FSM simplification David Harris 2021-07-17 11:41:43 -0400
  • 4469b5a4b3 hptw: default state should be unreachable David Harris 2021-07-17 11:33:16 -0400
  • 9cee6c2281 hptw: factored Misaligned David Harris 2021-07-17 11:31:16 -0400
  • fa12727bbb hptw: factored HPTWRead David Harris 2021-07-17 11:25:59 -0400
  • 708f8cc3a2 hptw: factored HPTWRead David Harris 2021-07-17 11:25:52 -0400
  • ef63e1ab52 hptw: factored pregen David Harris 2021-07-17 11:11:10 -0400
  • 880aa1c03a HPTW: more cleanup David Harris 2021-07-17 04:55:01 -0400
  • a0f6c9aec1 HPTW: factored out DTLBWrite/ITLBWrite David Harris 2021-07-17 04:44:23 -0400
  • 08e494dd7d HPTW: factored out PageTableENtry David Harris 2021-07-17 04:40:01 -0400
  • bd270acdb6 more cleaning up FSM David Harris 2021-07-17 04:35:51 -0400
  • 6d8a6eeba0 cleaning up FSM David Harris 2021-07-17 04:26:41 -0400
  • 26cd57aae0 merged hptw David Harris 2021-07-17 04:19:37 -0400
  • 330e500442 Simplify FSM David Harris 2021-07-17 04:12:31 -0400
  • 03ef3f7f17 Pulled TranslationPAdr mux out of HPTW FSM David Harris 2021-07-17 04:06:26 -0400
  • 5698433463 Simplified bad PTE detection David Harris 2021-07-17 03:30:17 -0400
  • ac67342dd4 Pulled out shared PTEReg David Harris 2021-07-17 03:21:09 -0400
  • 86ca9abe42 Flip-flop clean-up David Harris 2021-07-17 03:15:47 -0400
  • 9a15a2f7df Flip-flop clean-up David Harris 2021-07-17 03:12:24 -0400
  • 8241dd4599 Flip-flop clean-up David Harris 2021-07-17 03:10:17 -0400
  • 37691b84d0 Flip-flop clean-up David Harris 2021-07-17 02:59:35 -0400
  • a8a5fa4b3c Started pagetablewalker cleanup: combined state flops shared for both RV versions David Harris 2021-07-17 02:53:52 -0400
  • b65788d165 Replaced separate PageTypeF and PageTypeM with common PageType David Harris 2021-07-17 02:31:23 -0400
  • dac22d5016 Removed more unused signals from ahblite David Harris 2021-07-17 02:21:54 -0400
  • a898bbb991 Removed rest of HRDATAW from ahblite David Harris 2021-07-17 02:15:24 -0400
  • a19d3f126f Commented out HRDATAW logic in ebu David Harris 2021-07-17 02:10:57 -0400
  • e3dc59c5a2 renamed or_rows.sv David Harris 2021-07-16 20:17:03 -0400
  • 1bd5c137a6 Reduced size of physical memory by 16 for performance David Harris 2021-07-16 20:10:12 -0400
  • ec65c078e2 Updated location to find compiler for coremark Abe 2021-07-16 19:13:18 -0400
  • d10fd25c33 included virtual memory tests in testbench Kip Macsai-Goren 2021-07-16 17:57:24 -0400
  • f7a7dede77 removed old unused tests and outputs Kip Macsai-Goren 2021-07-16 17:46:51 -0400
  • 0084b086aa added backup reference output for sv32 Kip Macsai-Goren 2021-07-16 17:46:16 -0400
  • cc067f6afc removed execution tests until fences are implemented Kip Macsai-Goren 2021-07-16 17:45:54 -0400
  • 7d1504be89 added backup output files for when execution tests are possible Kip Macsai-Goren 2021-07-16 17:25:40 -0400
  • d945ba8975 removed execution tests until fences are implemented Kip Macsai-Goren 2021-07-16 17:24:59 -0400
  • c850ae0d99 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-16 15:59:13 -0500
  • 4a2da2035e More fixes to bring physical address into dtim range Kip Macsai-Goren 2021-07-16 16:58:28 -0400
  • 0b3dc288ec Made furture progress in the mmu tests. Ross Thompson 2021-07-16 15:56:06 -0500
  • dec15e7b90 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-16 16:05:50 -0400
  • 698afb0e79 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-16 15:04:38 -0500
  • 5e18a15a4c Added guide for Ben to do linux conversion. Ross Thompson 2021-07-16 15:04:30 -0500
  • 70fa6bca8e removed exectution tests that intentionally fail as well until fences are implemented. Kip Macsai-Goren 2021-07-16 15:47:08 -0400
  • 6c21c7903a removed execution tests that are supposed to pass until fences are implemented. Kip Macsai-Goren 2021-07-16 15:10:39 -0400
  • 6521d2b468 Also changed the shadow ram's dcache copy widths. Merge branch 'dcache' into main Ross Thompson 2021-07-16 14:21:09 -0500
  • 1aabee0478 Updated the config so the tim has a bigger range. Ross Thompson 2021-07-16 12:35:00 -0500
  • b3bf04d474 Updated wave file. Ross Thompson 2021-07-16 12:34:37 -0500
  • 46bce70e42 Fixed walker fault interaction with dcache. Ross Thompson 2021-07-16 12:22:13 -0500
  • b0fcfc2773 reduce number of UART ports to 1 bbracker 2021-07-16 12:42:29 -0400
  • f9d9d348d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-16 12:27:25 -0400
  • 01ca22af49 changed stop of linux boot from arch_cpu_idle to do_idle bbracker 2021-07-16 12:27:15 -0400
  • e0f719d513 Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. Ross Thompson 2021-07-16 11:12:57 -0500
  • ae7d48c326 incremental linux config de-bloating bbracker 2021-07-16 12:08:58 -0400
  • 40352ab7e4 incremental linux config de-bloating bbracker 2021-07-16 11:33:11 -0400
  • b1fe4ff295 incremental linux config de-bloating bbracker 2021-07-16 11:15:25 -0400
  • f34e28d187 incremental linux config de-bloating bbracker 2021-07-16 01:58:21 -0400
  • 3bcc5808d4 incremental linux config de-bloating bbracker 2021-07-16 01:54:36 -0400
  • ff90e6744c incremental linux config de-bloating bbracker 2021-07-16 01:43:16 -0400
  • ca5a1755f3 incremental linux config de-bloating bbracker 2021-07-16 01:33:51 -0400
  • b003c651be incremental linux config de-bloating bbracker 2021-07-16 01:25:41 -0400
  • ae886b015d incremental linux config de-bloating bbracker 2021-07-16 01:00:12 -0400
  • 7340e089f7 incremental linux config de-bloating bbracker 2021-07-16 00:46:22 -0400
  • c4716af4d6 incremental linux config de-bloating bbracker 2021-07-16 00:41:18 -0400
  • 0238b869fb incremental linux config de-bloating bbracker 2021-07-16 00:34:41 -0400
  • 3273b030e1 incremental linux config de-bloating bbracker 2021-07-16 00:16:12 -0400
  • 66bf2005fe incremental linux config de-bloating bbracker 2021-07-16 00:10:31 -0400
  • 4734f0eee5 incremental linux config de-bloating bbracker 2021-07-15 23:53:15 -0400
  • e565adfece incremental linux config de-bloating bbracker 2021-07-15 23:30:24 -0400
  • 3ff723493f incremental linux config de-bloating bbracker 2021-07-15 23:12:21 -0400
  • 8586462ee5 incremental linux config de-bloating bbracker 2021-07-15 23:00:20 -0400
  • 03e0bdaa5a incremental linux config de-bloating bbracker 2021-07-15 21:33:52 -0400
  • e922732fc5 incremental linux config de-bloating bbracker 2021-07-15 20:54:36 -0400
  • ca63f6bc48 fixed output file to match sv48 test again Kip Macsai-Goren 2021-07-15 18:55:00 -0400
  • c2535308fd working linux config bbracker 2021-07-15 18:49:54 -0400
  • 473ed689a2 fixed another address to be in tim range Kip Macsai-Goren 2021-07-15 18:31:53 -0400
  • abd5b1c02d Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. Kip Macsai-Goren 2021-07-15 18:30:29 -0400
  • 3b6291b734 stripped down busybox a bit bbracker 2021-07-15 16:07:56 -0400
  • 9aedfafb3c modified sv48 test to only read or write from physical addresses located in the dtim range from 0x80000000 to 0x87FFFFFF Kip Macsai-Goren 2021-07-15 14:01:29 -0400
  • e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. Ross Thompson 2021-07-15 11:56:35 -0500
  • fa26aec588 Merge branch 'main' into dcache Ross Thompson 2021-07-15 11:55:20 -0500
  • fd1de6b047 Updated wave file. Ross Thompson 2021-07-15 11:04:49 -0500
  • b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. Ross Thompson 2021-07-15 11:00:42 -0500
  • 8610ef204c Renamed DCacheStall to LSUStall in hart and hazard. Added missing logic in lsu. Ross Thompson 2021-07-15 10:16:16 -0500
  • 74e67df080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-15 10:52:39 -0400
  • 704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. Ross Thompson 2021-07-14 23:08:07 -0500
  • ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. Still not working fully. Ross Thompson 2021-07-14 22:26:07 -0500
  • c74d26eea4 Fixed lint warning Katherine Parry 2021-07-14 21:24:48 -0400
  • c79650b508 Added d cache StallW checks for any time the cache wants to go to STATE_READY. Ross Thompson 2021-07-14 17:25:50 -0500
  • 2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. Ross Thompson 2021-07-14 17:23:28 -0500
  • f5bfdf46db fpu unpacking unit created Katherine Parry 2021-07-14 17:56:49 -0400
  • dd313d57c0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-14 17:30:45 -0400
  • e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. Ross Thompson 2021-07-14 16:18:09 -0500
  • adce800041 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. Ross Thompson 2021-07-14 15:47:38 -0500