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  • 010339fa05 attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly bbracker 2021-12-07 11:16:43 -0800
  • 4dbd5d45ee Added information on how to copy the linux image to flash card. Ross Thompson 2021-12-07 13:16:38 -0600
  • 2229e66d6c add buildroot tv linking to make-tests.sh bbracker 2021-12-07 11:15:59 -0800
  • 6c6b7865fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-07 13:12:59 -0600
  • 22721dd923 Added generate around the dtim preload. Added readme to explain FPGA. Ross Thompson 2021-12-07 13:12:47 -0600
  • 29743c5e9e Fixed two issues. First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly. Second the bidir buffer for the sd card was connected backwards. Ross Thompson 2021-12-07 12:15:50 -0600
  • 5a73ecd0be regression.py bugfix bbracker 2021-12-06 19:32:38 -0800
  • 4df9093a7f add make-tests scripts bbracker 2021-12-06 15:37:33 -0800
  • 7c44ecb364 add buildroot-only option to regression bbracker 2021-12-06 14:13:58 -0800
  • 524bb0aa9a linux-testvectors symlinks shouldn't be in repo, especially not in this location bbracker 2021-12-05 22:03:51 -0800
  • c3c9c327b7 Fixed more constraint issues in fpga. Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim. Ross Thompson 2021-12-05 15:14:18 -0600
  • 7f5b993ea5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-12-05 20:04:46 +0000
  • f45fe48158 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-04 20:26:01 -0800
  • 64f33161bc Added files to repo David Harris 2021-12-04 20:25:33 -0800
  • 3f692ac89a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-03 17:56:00 -0600
  • 955ddcfbe1 Fixed bug in the top level of fpga verilog. Ross Thompson 2021-12-03 17:55:36 -0600
  • 5b4ff4526e Fixed a bunch of fpga issues. Ross Thompson 2021-12-03 17:47:54 -0600
  • 546f7fb4c2 fix some interrupt timing bugs Skylar Litz 2021-12-03 12:32:38 -0800
  • 8efce35f87 Edited the chenge privilege mode tests for clarity of use Kip Macsai-Goren 2021-12-03 10:07:37 -0800
  • df918d8ca0 added corrected exectue tests to pmp tests Kip Macsai-Goren 2021-12-03 10:00:57 -0800
  • cbb5e4440f Improved FPGA makefile and fixed timing constraints in clock converter. Ross Thompson 2021-12-03 10:05:13 -0600
  • 500e6ff430 Fixed buildroot to work with the fpga's merge. Ross Thompson 2021-12-02 18:09:43 -0600
  • b03ca464f1 Mostly integrated FPGA flow into main branch. Not all tests passing yet. Ross Thompson 2021-12-02 17:47:46 -0600
  • 9ccc8e7f3a Merge branch 'fpga' into main Ross Thompson 2021-12-02 14:28:10 -0600
  • 96fb3acefd Constraints for fpga are still wrong. Ross Thompson 2021-12-02 14:23:21 -0600
  • 5164129172 .* resolved in ifu.sv kwan 2021-12-02 10:32:35 -0800
  • 05a838aee2 .* in ifu/ifu.sv eliminated kwan 2021-12-02 09:45:55 -0800
  • 303324d370 Added tcl commands to build the implementation. Ross Thompson 2021-12-02 10:17:30 -0600
  • 0d47749cb5 Separated timing constraints from ILA. Ross Thompson 2021-12-01 18:15:04 -0600
  • e94fb2aaec Got fpga synthesis running from scripts. Ross Thompson 2021-12-01 16:59:04 -0600
  • 3b0989125f Merged makefile changes David Harris 2021-12-01 10:39:26 -0800
  • ca1d0cf12e Makefile organization David Harris 2021-12-01 10:38:46 -0800
  • 67eabfdacc Makefile cleaning Kevin Kim 2021-12-01 10:06:54 -0800
  • 42780ba40b Added coremark scripts to regression directory David Harris 2021-12-01 09:08:06 -0800
  • 6874697451 Updated Makefile David Harris 2021-12-01 09:06:33 -0800
  • ea979c7277 Makefile up and running Kevin Kim 2021-11-30 23:02:02 -0800
  • 9a5b9922fa changed readme to reflect submodule updates Kevin Kim 2021-11-30 18:26:49 -0800
  • cae3a44b9a added arch-test submodule Kevin Kim 2021-11-30 18:22:08 -0800
  • b5e86b2e20 Added git submodules -riscv-arch-test -rscv-isa-sim submodules are added in addins/ directory Kevin Kim 2021-11-30 18:16:37 -0800
  • 5ea9ec0ae6 Created top level FPGA module which replicates the schematic of the initial fpga design. Ross Thompson 2021-11-30 17:18:28 -0600
  • a146d7a618 testing push David Harris 2021-11-30 11:20:09 -0800
  • ce50b1010d Coremark updates David Harris 2021-11-30 11:16:13 -0800
  • d5f445e0fd Added make clean to fpga IP generator. Ross Thompson 2021-11-29 18:42:28 -0600
  • a528a86607 Created Makefile to manage IP generation. Ross Thompson 2021-11-29 18:32:51 -0600
  • 51807379a8 Added final IP generator script (proc_sys_reset). Ross Thompson 2021-11-29 17:43:47 -0600
  • 97c73f10ff Fixed uart for FPGA config after merge. This still needs some work. Ross Thompson 2021-11-29 16:07:54 -0600
  • 8aa87958a9 Added ddr4 generator script. Ross Thompson 2021-11-29 15:56:57 -0600
  • bb2bde2743 coremark makefile David Harris 2021-11-29 13:33:01 -0800
  • da4ed957aa Created tcl scripts to build 2 of the 4 xilinx IP. Ross Thompson 2021-11-29 11:26:08 -0600
  • a871118116 Merge branch 'main' into fpga Ross Thompson 2021-11-29 10:10:37 -0600
  • 5642918ead Merge branch 'main' into fpga Ross Thompson 2021-11-29 10:06:53 -0600
  • fed0bb08d6 UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses bbracker 2021-11-25 11:01:59 -0800
  • 09d3322a26 updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well Noah Limpert 2021-11-24 23:22:04 -0800
  • 93b626ce2a replaced .* instation of priv module on wallypiplinedhart Noah Limpert 2021-11-24 22:58:59 -0800
  • f36cc7a2a3 Made abhlite instation on wallypipehart more clear, updated spacing for consistency Noah Limpert 2021-11-24 22:48:01 -0800
  • 5b7c969170 updated module instation of LSU on wallypiplinedhard Noah Limpert 2021-11-24 22:09:39 -0800
  • 23194c0308 fix parseState.py to correctly take in PMPCFG bbracker 2021-11-24 16:52:51 -0800
  • 1183aed049 Missed another change to uart. Ross Thompson 2021-11-23 10:07:14 -0600
  • 3fc370654d Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. Ross Thompson 2021-11-23 10:00:32 -0600
  • f12e7e1b68 Added QEMU hack for initial LCR value in uart. Ross Thompson 2021-11-22 15:23:19 -0600
  • f05a66acd1 Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed. Ross Thompson 2021-11-22 15:20:54 -0600
  • d5cf6da6eb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-11-22 11:30:14 -0600
  • cffb72042a activate STVAL for buildroot bbracker 2021-11-21 10:40:28 -0800
  • e955b17500 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-11-20 22:44:45 -0600
  • 055a5bd202 Removed unneeded check for icache ways. Ross Thompson 2021-11-20 22:44:37 -0600
  • 9d3261ed49 Reversed bit order in uart. Ross Thompson 2021-11-20 22:42:47 -0600
  • 88b4e0946f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-11-20 22:37:15 -0600
  • 705572f0ac Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table walk should be aborted before starting. Ross Thompson 2021-11-20 22:35:47 -0600
  • 4e96d0f1db add checkpoints to regression bbracker 2021-11-20 19:42:53 -0800
  • cf27cc7fcd increase niceness of automatic checkpoint generation bbracker 2021-11-20 12:48:23 -0800
  • e5d3416258 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-11-19 20:25:06 -0800
  • 713aa7faac automatic bug finder script bbracker 2021-11-19 20:25:00 -0800
  • c07caf4fe8 increase buildroot progress expecttions; increase timeout to 20 hours bbracker 2021-11-19 12:52:11 -0800
  • 4d1bb3cdd8 Coremark Diretory cleanup, removed syscall warning about noreturn, rresults are good. David Harris 2021-11-19 07:39:15 -0800
  • 82cfebfb83 Coremark Cleanup, trying compile from addins David Harris 2021-11-19 06:09:04 -0800
  • bc62dcb57a Replaced build-coremark.sh with Makefile David Harris 2021-11-18 20:46:59 -0800
  • 5b424fe9bf exe2memfile don't print when only 1 file David Harris 2021-11-18 20:37:53 -0800
  • a801e0dbec Moved exe2memfile.pl David Harris 2021-11-18 20:32:13 -0800
  • d1b3e85f14 CoreMark cleanup David Harris 2021-11-18 20:23:55 -0800
  • 690410721d Cleaning up CoreMark benchmark David Harris 2021-11-18 20:12:52 -0800
  • 8e8b84f532 vert "Simplifying riscv-coremark" David Harris 2021-11-18 18:40:13 -0800
  • ce8232e396 Simplifying riscv-coremark David Harris 2021-11-18 17:15:40 -0800
  • b73e6354e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-11-18 16:14:42 -0800
  • 402b473dbb CoreMark testing David Harris 2021-11-18 16:14:25 -0800
  • 0bf1836a3a Removed .* from hazard hzu(.*). slmnemo 2021-11-17 14:21:23 -0800
  • 5c28553ca1 Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. slmnemo 2021-11-17 14:08:08 -0800
  • df6c54a664 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main slmnemo 2021-11-17 13:38:51 -0800
  • bf8cef78bc removed .* from muldiv.sv (REAL) slmnemo 2021-11-17 13:37:50 -0800
  • 0a281a06e0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-11-17 13:28:33 -0800
  • b63c0f35d1 ieu variable naming changed for clarity Noah Limpert 2021-11-17 13:24:28 -0800
  • c5c886ddc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main slmnemo 2021-11-17 13:23:20 -0800
  • 40efffc70b Removed .*s from muldiv.sv slmnemo 2021-11-17 13:23:12 -0800
  • bbd17e730b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Noah Limpert 2021-11-17 13:04:33 -0800
  • 70a84b56c8 Updated IFU variable naming for clarity Noah Limpert 2021-11-17 12:39:05 -0800
  • 6437c04074 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kevin Kim 2021-11-17 12:18:25 -0800
  • 38437c664e root level makefile added Kevin Kim 2021-11-17 12:17:56 -0800
  • 7a8c21e71f renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv Kip Macsai-Goren 2021-11-17 10:53:17 -0800
  • f4c221f20a Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. Ross Thompson 2021-11-17 12:47:19 -0600
  • 86ff349baf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main slmnemo 2021-11-17 10:39:52 -0800
  • 129b9721d6 Removed .* from muldiv. slmnemo 2021-11-17 10:39:18 -0800