David Harris
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ac1b1bfbb6
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update scripts for handling src/*/* subdirectories
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2021-10-23 08:54:29 -07:00 |
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David Harris
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3249d65209
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Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
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2021-10-23 06:15:26 -07:00 |
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David Harris
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75c17dc372
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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David Harris
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42d573be57
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SRT Division unsigned passing Imperas tests
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2021-09-30 12:17:24 -04:00 |
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Ross Thompson
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74fba4bb06
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Moved the test bench modules to a common directory.
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2021-07-30 14:16:14 -05:00 |
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David Harris
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0674f5506e
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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bbracker
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39ae743543
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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bbracker
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a3487a9e47
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do script refactor
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2021-04-24 09:32:09 -04:00 |
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bbracker
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755e2e5771
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merge testbench
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2021-04-08 14:28:01 -04:00 |
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ushakya22
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6b9ae41302
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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bbracker
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85363e941d
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AHB bugfixes and sim waveview refactoring
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2021-03-18 18:25:12 -04:00 |
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Teo Ene
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4fd0ecff69
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Temporarily reverted my last few commits
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2021-03-17 15:16:01 -05:00 |
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Ross Thompson
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4c8952de6a
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Converted branch predictor preloads to use system verilog rather than modelsim's load command.
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2021-03-15 12:39:44 -05:00 |
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Ross Thompson
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845115302e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-10 15:37:02 -06:00 |
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Ross Thompson
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50a92247b3
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Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
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2021-03-10 11:00:51 -06:00 |
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David Harris
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17c0f9629a
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WALLY-LRSC atomic test passing
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2021-03-09 09:28:25 -05:00 |
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Ross Thompson
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301166d062
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Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
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2021-03-05 15:23:53 -06:00 |
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Ross Thompson
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66e84f3a2c
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Merge branch 'bp' into main
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
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2021-03-04 13:35:46 -06:00 |
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David Harris
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cf03afa880
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Eliminated flushing pipeline on CSR reads
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2021-02-26 17:00:07 -05:00 |
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Teo Ene
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c47872c2af
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Changed .do file back to run all
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2021-02-25 09:58:54 -06:00 |
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Ross Thompson
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5df7e959f3
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Integrated the branch predictor into the hardward. Not yet working.
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2021-02-17 22:19:17 -06:00 |
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David Harris
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2357f5513b
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Debugging instruction fetch
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2021-02-09 11:02:17 -05:00 |
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David Harris
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3551cc859b
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Data memory bus integration
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2021-02-07 23:21:55 -05:00 |
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David Harris
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396cea1ea7
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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David Harris
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a357f2a0e7
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Connected AHB bus to Uncore
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2021-01-29 23:43:48 -05:00 |
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David Harris
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dc2443c55b
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Moving data memory to uncore
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2021-01-29 15:37:51 -05:00 |
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David Harris
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824014c5c0
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Repartitioned with Instruction Fetch Unit, Integer Execution Unit
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2021-01-27 22:49:47 -05:00 |
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David Harris
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b88508ca11
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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David Harris
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fa18052348
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Added test configurations
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2021-01-25 11:28:43 -05:00 |
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