Ross Thompson
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fea439b84d
|
SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
|
David Harris
|
9ae25b0cea
|
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
|
Ross Thompson
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86fbe2a654
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Changed configs to support 4 ways set associative caches.
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2021-09-08 12:52:49 -05:00 |
|
Ross Thompson
|
c749d08542
|
fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
|
David Harris
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e1a1a8395e
|
Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
|
David Harris
|
4d40b5faef
|
Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
|
David Harris
|
8d348dacce
|
Started atomics
|
2021-07-17 21:11:41 -04:00 |
|
David Harris
|
1bd5c137a6
|
Reduced size of physical memory by 16 for performance
|
2021-07-16 20:10:12 -04:00 |
|
Ross Thompson
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6521d2b468
|
Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
|
David Harris
|
80666f0a71
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Added ASID & Global PTE handling to TLB CAM
|
2021-07-04 17:52:00 -04:00 |
|
David Harris
|
9645b023c9
|
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Kip Macsai-Goren
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d7e518991e
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
|
2021-06-24 20:01:11 -04:00 |
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bbracker
|
23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
|
2021-06-20 22:38:25 -04:00 |
|
David Harris
|
35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
|
2021-06-18 08:05:50 -04:00 |
|
David Harris
|
da8eb7749f
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Started simplifying PMA checker
|
2021-06-17 16:28:06 -04:00 |
|
David Harris
|
0ffbd03139
|
More verilator fixes, but bpred is broken
|
2021-06-09 21:03:03 -04:00 |
|
David Harris
|
2952550db7
|
More PMP entries
|
2021-06-08 15:33:06 -04:00 |
|
David Harris
|
90e5781471
|
Start to parameterize number of PMP Entries
|
2021-06-08 15:29:22 -04:00 |
|
Kip Macsai-Goren
|
a95a7a7b82
|
working version with new mmu comments, old boottim values
|
2021-06-08 15:20:25 -04:00 |
|
David Harris
|
b613f46c2d
|
Resized BOOT TIM to 1 KB
|
2021-06-08 14:04:32 -04:00 |
|
David Harris
|
2ae5ca19b5
|
Continued merge
|
2021-06-07 12:49:47 -04:00 |
|
David Harris
|
ff62000e2c
|
Second attept to commit refactoring config files
|
2021-06-07 12:37:46 -04:00 |
|
David Harris
|
dc0b19dfaa
|
Merge difficulties
|
2021-06-07 09:50:23 -04:00 |
|
David Harris
|
d5ec797ba4
|
Refactored configuration files and renamed testbench-busybear to testbench-linux
|
2021-06-07 09:46:52 -04:00 |
|
Kip Macsai-Goren
|
22e8e06ac7
|
moved privilege dfinitions into wally-constants, upgraded relevant includes
|
2021-06-04 17:55:07 -04:00 |
|
David Harris
|
a26bf37be8
|
Started MMU
|
2021-06-04 11:59:14 -04:00 |
|
Shriya Nadgauda
|
c5a306426a
|
finishing merge conflict changes
|
2021-05-03 22:15:05 -04:00 |
|
Shriya Nadgauda
|
b7159652f6
|
merge conflict fixes
|
2021-05-03 22:12:30 -04:00 |
|
Shriya Nadgauda
|
968994c04a
|
updated pipeline tests
|
2021-05-03 22:07:36 -04:00 |
|
bbracker
|
1fcd43e844
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-30 06:26:35 -04:00 |
|
bbracker
|
182bfdbb0e
|
rv32 plic test and lint fixes
|
2021-04-30 06:26:31 -04:00 |
|
Ross Thompson
|
818c0abc89
|
Fixed memory size in configs for rv32ic and rv64ic.
Removed warning on call to $fscanf.
|
2021-04-29 17:36:46 -05:00 |
|
Ross Thompson
|
72363f5c66
|
Added the ability to exclude branch predictor.
|
2021-04-26 14:27:42 -05:00 |
|
bbracker
|
74b35ac57a
|
greatly improved PLIC register interface
|
2021-04-22 11:22:01 -04:00 |
|
Noah Boorstin
|
6954e6df4c
|
buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
|
2021-04-17 14:44:32 -04:00 |
|
bbracker
|
290b3424e5
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-04-15 21:09:27 -04:00 |
|
bbracker
|
368c94d4ff
|
working GPIO interrupt demo
|
2021-04-15 21:09:15 -04:00 |
|
Domenico Ottolia
|
92bb38fa8c
|
Add support for vectored interrupts
|
2021-04-15 19:13:42 -04:00 |
|
Shreya Sanghai
|
0369fc5d1e
|
Cherry Pick merge of Shreya's localhistory predictor changes into main.
fixed minor bugs in localHistory
|
2021-04-15 09:04:36 -05:00 |
|
bbracker
|
31c6b2d01f
|
Yee hoo first draft of PLIC plus self-checking tests
|
2021-04-04 06:40:53 -04:00 |
|
Thomas Fleming
|
7126ab7864
|
Complete basic page table walker
|
2021-03-30 22:19:27 -04:00 |
|
bbracker
|
11d4a8ab34
|
first pass at PLIC interface
|
2021-03-22 10:14:21 -04:00 |
|
Shreya Sanghai
|
bbe0957df5
|
Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
|
2021-03-18 17:25:48 -04:00 |
|
Ross Thompson
|
1091dd10c1
|
Switched to gshare from global history.
Fixed a few minor bugs.
|
2021-03-18 16:05:59 -05:00 |
|
Noah Boorstin
|
bc1a0c6ee7
|
change ifndef to generate/if
|
2021-03-18 12:50:19 -04:00 |
|
Noah Boorstin
|
a2b0af460e
|
everyone gets a bootram
|
2021-03-18 12:35:37 -04:00 |
|
Shreya Sanghai
|
36f0631203
|
added gshare and global history predictor
|
2021-03-16 17:03:01 -04:00 |
|
Shreya Sanghai
|
9eed875886
|
added global history branch predictor
|
2021-03-16 16:06:40 -04:00 |
|
Shreya Sanghai
|
74f1641c5a
|
Merge branch 'counters' into main
added a configurable number of performance counters
|
2021-03-16 11:01:30 -04:00 |
|
Ross Thompson
|
4c8952de6a
|
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
|
2021-03-15 12:39:44 -05:00 |
|