Thomas Fleming
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fc39535e4e
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Refactor TLB into multiple files
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2021-04-08 03:24:10 -04:00 |
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Thomas Fleming
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c54aecde73
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Provide attribution link for priority encoder
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2021-04-08 03:05:06 -04:00 |
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Thomas Fleming
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303c2c4839
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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bbracker
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38017e6aae
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declare memread signal
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2021-04-05 08:13:01 -04:00 |
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bbracker
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a4c3afb847
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PLIC claim reg side effects now check for memread signal
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2021-04-05 08:03:14 -04:00 |
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bbracker
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4a5aa5b202
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plic subword access compliance
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2021-04-04 23:10:33 -04:00 |
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Katherine Parry
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e6a7353847
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Added missing files in FPU
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2021-04-04 18:09:13 +00:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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Thomas Fleming
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6b43381c38
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Comment out fpu from hart until module exists
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2021-04-03 22:34:11 -04:00 |
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Thomas Fleming
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dbd5a4320e
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Merge branch 'mmu' into main
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
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2021-04-03 22:12:52 -04:00 |
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Thomas Fleming
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8dfec29f7e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-03 22:09:50 -04:00 |
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Thomas Fleming
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1cbdaf1f05
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Fix extraneous page fault stall
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2021-04-03 21:28:24 -04:00 |
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Katherine Parry
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d7b1379ab8
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Integrated FPU
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2021-04-03 20:52:26 +00:00 |
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Ross Thompson
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d21006d048
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Partial fix to the integer divide stall issue.
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2021-04-02 15:32:15 -05:00 |
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James E. Stine
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362f6ea2e6
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Minor cleanup
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2021-04-02 08:20:44 -05:00 |
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James E. Stine
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cff08adc3a
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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Thomas Fleming
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bfb4b051c6
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Merge branch 'main' into mmu
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2021-04-01 16:29:39 -04:00 |
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Thomas Fleming
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350fe87119
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-01 16:24:06 -04:00 |
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Thomas Fleming
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fdb20ee1cf
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Implement sfence.vma and fix tlb writing
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2021-04-01 15:55:05 -04:00 |
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James E. Stine
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0495195d68
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Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
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2021-04-01 12:30:37 -05:00 |
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Thomas Fleming
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77b8e27205
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Disable 'always-on' virtual memory
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2021-03-30 22:49:47 -04:00 |
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Thomas Fleming
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eca2427f94
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Merge remote-tracking branch 'origin/main' into main
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
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2021-03-30 22:24:47 -04:00 |
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Thomas Fleming
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7126ab7864
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Complete basic page table walker
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2021-03-30 22:19:27 -04:00 |
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ushakya22
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6b9ae41302
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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Brett Mathis
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162f2df880
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FPU Pipeline completed - can begin integration
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2021-03-25 13:29:03 -05:00 |
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Thomas Fleming
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e3900bd0fa
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Finish finite state machines for page table walker
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2021-03-25 02:48:40 -04:00 |
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Thomas Fleming
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b5003b093a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-25 02:35:21 -04:00 |
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bbracker
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a3788eb218
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added 1 tick delay to dtim flops
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2021-03-25 02:23:30 -04:00 |
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bbracker
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02e924e55a
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instrfaults not respecting stalls bugfix
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2021-03-25 00:16:26 -04:00 |
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bbracker
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1e3f683a9d
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upgraded gpio bus interface
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2021-03-25 00:15:02 -04:00 |
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bbracker
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e98dd420bc
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future work comment about suspicious-looking verilog in csri.sv
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2021-03-25 00:10:44 -04:00 |
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Thomas Fleming
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b1d849c822
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Add all PMP addr registers
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2021-03-24 21:58:33 -04:00 |
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Katherine Parry
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18cb1f4873
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fixed various bugs in the FMA
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2021-03-24 21:51:17 +00:00 |
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Katherine Parry
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56dc8de009
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fixed various bugs in the FMA
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2021-03-24 01:35:32 +00:00 |
|
Teo Ene
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ef3d2dda48
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Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem
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2021-03-23 15:21:13 -05:00 |
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Shreya Sanghai
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1d6a2989ed
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PC counts branch instructions
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2021-03-23 14:25:51 -04:00 |
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bbracker
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5efd5958e7
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added delays to uart AHB signals
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2021-03-22 15:40:29 -04:00 |
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bbracker
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11d4a8ab34
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Katherine Parry
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f741ba7702
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fixed various bugs in the FMA
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2021-03-21 22:53:04 +00:00 |
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Katherine Parry
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e317e7511e
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messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic
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2021-03-20 02:05:16 +00:00 |
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bbracker
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85363e941d
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AHB bugfixes and sim waveview refactoring
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2021-03-18 18:25:12 -04:00 |
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Shreya Sanghai
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bbe0957df5
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Ross Thompson
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1091dd10c1
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Switched to gshare from global history.
Fixed a few minor bugs.
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2021-03-18 16:05:59 -05:00 |
|
Ross Thompson
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8f4051543c
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Fixed minor bug with the size of gshare.
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2021-03-18 16:00:09 -05:00 |
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Shreya Sanghai
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eb86bfc084
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removed unnecesary PC registers in ifu
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2021-03-18 16:31:21 -04:00 |
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Thomas Fleming
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8d484174a7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-18 14:36:42 -04:00 |
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Thomas Fleming
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7f7597e667
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Connect tlb, pagetablewalker, and memory
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2021-03-18 14:35:46 -04:00 |
|
Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
|
Noah Boorstin
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a2b0af460e
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everyone gets a bootram
|
2021-03-18 12:35:37 -04:00 |
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Shreya Sanghai
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36f0631203
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added gshare and global history predictor
|
2021-03-16 17:03:01 -04:00 |
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