Xavi/cvw
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47 Commits

Author SHA1 Message Date
Ross Thompson
442de3f5b7 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
a4822c9f54 Added license and comments to new script. 2023-01-20 19:50:33 -06:00
Ross Thompson
b709c224ab Updated ignore to exclude copied files. 2023-01-20 19:47:33 -06:00
Ross Thompson
e06237ad92 Removed mark_debug vivado directive from source code. 
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
 2023-01-20 19:43:18 -06:00
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
b7224cc5ba Updated fpga constraints. 2022-12-21 14:50:01 -06:00
Ross Thompson
8692bafd04 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
3de5144ae4 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
fd1ef82310 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Ross Thompson
1510c2d92f Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
ae01c8e824 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
962ba5e4b8 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
c7055a3ee2 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
Ross Thompson
471f204c48 Added bootrom.txt. 2022-03-30 17:29:48 -05:00
Ross Thompson
c88541cf6b test. 2022-03-28 17:04:58 -05:00
Ross Thompson
3b31d8f8fb Updated debug2 ila signal names. 2022-01-28 11:43:49 -06:00
Ross Thompson
840e814e95 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
bb11f5637c Added comport.setup to remind how to configure com port for xilinx fpga. 
Added load-deadlock.tsm to trigger load operation deadlock.
 2022-01-25 14:54:38 -06:00
David Harris
07425369fc Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
David Harris
6febce0001 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
Ross Thompson
0f14d2ec88 Added advanced Vivado debug scripts. 2022-01-07 17:56:40 -06:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Ross Thompson
a11597b6bd Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
6d2a4b8354 Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
68745d40f2 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
29743c5e9e Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
5b4ff4526e Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Ross Thompson
cbb5e4440f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
96fb3acefd Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
e94fb2aaec Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
Ross Thompson
d5f445e0fd Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
51807379a8 Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
8aa87958a9 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00
Ross Thompson
da4ed957aa Created tcl scripts to build 2 of the 4 xilinx IP. 2021-11-29 11:26:08 -06:00