Ross Thompson c3c9c327b7 Fixed more constraint issues in fpga. ... Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim.		2021-12-05 15:14:18 -06:00
..
Makefile	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
wally.tcl	Fixed more constraint issues in fpga.	2021-12-05 15:14:18 -06:00
xlnx_ahblite_axi_bridge.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00
xlnx_axi_clock_converter.tcl	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
xlnx_ddr4.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00
xlnx_proc_sys_reset.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00