15 Commits

Author	SHA1	Message	Date
Noah Boorstin	e5e345d161	busybear: instantiate normal wallypipelinedsoc	2021-02-28 06:02:21 +00:00
kaveh pezeshki	c7863d58cd	merged with main to integrate with AHB	2021-02-26 05:37:10 -08:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Noah Boorstin	ceb7df3561	busybear: instantiate soc instead of hart	2021-02-23 18:59:06 +00:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	2357f5513b	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	4fbb5f0f1b	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	056b147b13	Renamed DCU to DMEM	2021-02-01 18:52:22 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00