Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
292 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
3c5be59e9b
Go to file
Noah Boorstin 3c5be59e9b busybear: add branch preditor loading to do file 
(sorry to add more loading to the do instead of less)
2021-03-05 21:01:41 +00:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined busybear: add branch preditor loading to do file 2021-03-05 21:01:41 +00:00
.gitignore add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor