Ross Thompson
e29803be30
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
David Harris
bf9082b0ad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:09:20 -08:00
David Harris
475fa01767
Fixing paths in wally-setup.sh
2021-12-20 21:08:34 -08:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
David Harris
a25d541dcf
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
3c3bfd055e
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
225cd5a114
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
kwan
8f79a12cbb
priviledge .* removed, passed regression
2021-12-13 00:34:43 -08:00
kwan
f0e425e4ea
test
2021-12-13 00:31:51 -08:00
kwan
a365e86197
priviledge .* fixed, passed local regression
2021-12-13 00:22:01 -08:00
kwan
a95efea0b3
Priviledged .* removed
2021-12-12 09:55:45 -08:00
kwan
82bab8e90e
Privilige .*s removed
2021-12-12 09:54:14 -08:00
Ross Thompson
37079626cd
Fixed numerous errors in the preformance counter updates.
...
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
cffb72042a
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
David Harris
c0145c0a35
merging changes
2021-10-26 08:34:36 -07:00
David Harris
8287a1ef3e
Synchronous reset in non-flop blocks
2021-10-26 08:30:35 -07:00
bbracker
046a78a8fc
manually resolved git merge conflicts in testbench linux after checkpointing
2021-10-24 15:02:19 -07:00
bbracker
36b39358c6
add checkpointing to linux testbench
2021-10-24 06:47:35 -07:00
David Harris
62a23fe878
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
61fdb3d902
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
8e516e6391
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
2e796e3da2
lint cleanup: FPU and privileged
2021-10-23 09:41:24 -07:00
David Harris
c316bff15a
subword read and csrc lint cleanup
2021-10-23 09:29:15 -07:00
David Harris
28d8f6d5cf
FMA and CSRC lint cleanup
2021-10-23 09:20:24 -07:00
David Harris
e2e950ac0f
Cleaned up LINT erors
2021-10-23 06:28:49 -07:00
Ross Thompson
de4ea16d32
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
David Harris
3bc985d230
Changed some flops to settable
2021-10-18 17:05:29 -07:00
David Harris
0516ee768b
replaced flopenl with flopenr when clearing to 0
2021-10-18 16:53:18 -07:00
bbracker
6aa79657ed
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit fec96218f6
2021-09-30 20:45:26 -04:00
bbracker
fec96218f6
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
Ross Thompson
7ca801113e
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
9fa048980d
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
bbracker
bb84354a47
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
Ross Thompson
0cc47f3daf
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
c31b7b4dc5
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
2825074114
Confirmed David's changes to the interrupt code.
...
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
David Harris
4677b4bb38
possible interrupt code
2021-08-22 17:02:40 -04:00
Ross Thompson
55fda4de62
Switched ExceptionM to dcache to be just exceptions.
...
Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
c749d08542
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Kip Macsai-Goren
c69a5dc8a6
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
365485bd8b
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
bbracker
cd469035be
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
David Harris
a67292b5f3
trap.sv comment cleanup
2021-07-17 16:01:07 -04:00
David Harris
c1c3249709
trap.sv cleanup
2021-07-17 15:57:10 -04:00
David Harris
e182cac9bc
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:24:26 -04:00
David Harris
2f81e4c70d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
