Ross Thompson
1e2180ef98
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
179d321683
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
4e52755c9f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-22 18:07:32 -06:00
cturek
3fbccbf119
Updated testbench/wave for fdivsqrt new start signals
2022-11-22 22:22:26 +00:00
Ross Thompson
84679c0062
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
5800dfde60
Updated wave file.
2022-11-13 21:34:45 -06:00
Ross Thompson
7311eca5ff
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
49a85c7f50
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
David Harris
6ab6467777
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
1428081742
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
403daecc8e
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
36c0e1d4e9
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
b52f593ecb
Reorganized the configs.
2022-10-09 16:46:48 -05:00
Ross Thompson
8d01cf32fc
Updated wavefile.
2022-10-05 14:55:40 -05:00
Kip Macsai-Goren
c4441eb0fa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
175e824a61
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
47e936cab3
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
David Harris
f08d5b23d5
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
91fcca9d17
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
David Harris
8d1408a9d6
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
362056f53d
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
40e7d2648f
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
c2f81e309b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 11:11:39 -07:00
David Harris
b0cf73d19c
Running 16-bit square root cases first in testfloat
2022-09-07 11:11:35 -07:00
Ross Thompson
fd4b382ec6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 12:26:50 -05:00
Ross Thompson
54c55b57cb
Named change for ahb tests to be less annoying.
2022-09-07 12:24:41 -05:00
Ross Thompson
6581490f9c
Modified regression tests to add some ahb configurations.
2022-09-07 12:03:58 -05:00
David Harris
29f015810b
Added rv32i config for regression of wally32periph
2022-09-07 09:37:59 -07:00
Ross Thompson
d07c44bcf6
Merge branch 'multimanager' into main
2022-09-07 10:54:27 -05:00
David Harris
8438546d52
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
Ross Thompson
9d5a7281b8
Modified ram_ahb to work with different latencies.
2022-09-04 14:46:15 -05:00
David Harris
247ce70348
Fixed lint errors in square root and improved waveforms in testfloat
2022-09-01 15:49:13 -07:00
Ross Thompson
fcd1465de1
Renamed AHBCachebusdp to abhcacheinterface.
2022-08-31 14:12:19 -05:00
Ross Thompson
d06c64094b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-31 11:38:29 -05:00
Ross Thompson
5b8f888e21
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
ccb3e9e24e
Updates to wave file.
2022-08-30 17:34:36 -05:00
Ross Thompson
96793d15c0
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
2d6a6c6e44
Temporary commit.
2022-08-30 15:40:42 -05:00
Ross Thompson
63a824cca1
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba
Progress.
2022-08-30 14:17:00 -05:00
David Harris
5956fbdd62
Fixed checking termination in testfloat testbench
2022-08-30 10:55:21 -07:00
David Harris
81ec1ac858
Separated out radix 2 and radix 4 stages into different modules
2022-08-29 04:26:14 -07:00
David Harris
b4cb9a678a
renamed srt to fdivsqrt
2022-08-29 04:04:05 -07:00
David Harris
35d0a951d2
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
